ALU

Semiconductors

Designing for EMI Testing: A Step-by-Step Guide

Solve your EMI problems more efficiently with oscilloscope solutions

Download this free white paper and learn how to analyze EMI for more efficient R&D and  improved time-to-market.

Key take-aways:

  • Understand the basic steps involved in EMI testing
  • Learn to use probes to discover an inteference signal
  • Discover how to analyze the interference behavior using a digital oscilloscope

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DDR Memory Test Challenges from DDR3 to DDR4 and DDR5

Prepare for DDR5 Test Challenges

DDR memory chip technology has progressed through two generations in the past 10 years, and the next generation is currently being defined. Each of these generations improved in speed, efficiency, and memory capacity. Don’t get left behind—stay up to date on the DDR memory challenges that lie ahead!

Download the “DDR Memory – Test Challenges from DDR3 to DDR4 and DDR5” white paper to get tips on testing and learn about the latest test equipment.

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Practical Guide to Maximizing DC Measurement Performance

Download this white paper to learn how to use a source measure unit (SMU) to perform DC measurements.

Download this white paper to learn how to use a source measure unit (SMU) to perform DC measurements. This guide explores best practices in the context of common measurement scenarios, so you learn when and where to most effectively apply the concepts covered.

Key take-aways:

  • Discover the fundamentals of DC measurement instruments
  • Learn how to set up and use SMUs
  • Understand the key best practices to mitigate various errors seen when taking DC measurements

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Shielding Effectiveness of Expanded Metal Foils

Careful circuit design can minimize EMI, but additional shielding measures are often required.

Expanded metal foils are versatile, effective EMI shielding materials. EMFs are formed from thin metal foils, creating a lightweight, strong and flexible sheet material. Expanded copper foil is commonly used for EMI shielding, but aluminum, nickel, Monel and stainless-steel foils can also be used when there are unique specifications.

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Watlow acquires Yarbrough Solutions Worldwide

Watlow, a designer and manufacturer of complete thermal systems, announced that it has acquired Yarbrough Solutions Worldwide of Austin, Texas. Terms of the transaction were not disclosed.

Yarbrough is a semiconductor equipment solutions provider that services semiconductor fabrication companies globally by developing, installing and servicing high-performance solutions at its customer’s fabrication plants. In performing these services, Yarbrough has long relied upon a myriad of Watlow product offerings such as electric heaters, temperature sensors, temperature controllers and power controllers.

“Yarbrough is a known leader in providing innovative thermal system solutions to semiconductor equipment end users,” said Rob Gilmore, vice president and general manager of Watlow’s semiconductor business unit. “Adding Yarbrough’s know-how and expertise to Watlow’s world-class suite of thermal system capabilities enhances our ability to serve customers through the entire semiconductor fabrication process, from the tool to the scrubber, to ensure thermal optimization of the complete system.”

“This acquisition enables both parties to provide even more value to our semiconductor equipment customers,” said Pat Swayze, vice president of Yarbrough. “We are very excited about Watlow’s long-term vision and we look forward to contributing to the company’s future growth.”

A key element of the acquisition is a South Korean joint venture, which enhances Watlow’s presence in the region. This joint venture between Watlow and its partner, Global Standard Technology Co., Ltd., an established semiconductor business, will be named Watlow Pacific Inc.

Watlow has experienced significant recent growth and aspires to be the share leader in all of its core markets. According to Peter Desloge, Watlow’s president, chief executive officer and chairman, “Watlow is committed to the success of its customers through product and technology leadership, and this is one of the many reasons why the world’s leading companies begin with Watlow for their thermal needs. The Yarbrough acquisition is a continuation of Watlow’s strategy to combine organic investments and acquisitions to achieve consistent, sustainable long-term growth. This acquisition enhances our thermal control capabilities and our ability to create value and deliver a competitive advantage to our customers. We are very excited to welcome Yarbrough to the Watlow team.”

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TSMC WannaCry infection forces shutdowns, financial losses

By Christopher Morales, Head of Security Analytics, Vectra

On August 3, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), the largest chip fabricator globally introduced a WannaCry Ransomware cryptowormvariant onto its information technology/operational technology (IT/OT) networks. A TSMC supplier installed infected software on a new fabrication tool and connected it to the network, facilitating the malware infestation.

The infection spread quickly, taking out 10,000+ unpatched Windows 7 machines that run the chip fab company’s tool automation interface. The crypto worm crashed and rebooted systems endlessly, forcing several plants in Taichung, Hsinchu andTainan to shut down through much of the weekend.

The infection crippled materials handling systems and production equipment as well as Windows 7 computers. Some of the plants were producing SoC chips for the AppleiPhone 8 and X models. The incident’s connection to Apple and the iPhone heightened its visibility in the news media.

According to TSMC CEO C.C. Wei, patching for the Windows 7 machines requires computer downtime and collaboration with equipment suppliers. The absence of currentpatches created an environment where WannaCry could easily propagate.

The 2018 Spotlight Report on Manufacturing published by Vectra a few weeks before the incident foretold TSMC’s infection, which could cost the company as much as $255 million.

Smart manufacturer cybersecurity risks are increasing

According to the TSMC website, the company had “introduced new applications such as IoT, intelligent mobile devices and mobile robots to consolidate data collection, yield traceability, workflow efficiency, and material transportation to continuously enhance fab operation efficiency.” Further, TSMC had “integrated automatic manufacturing systems,” according to its website.

These innovations are typical in the evolution of Industry 4.0, which has increased the risk of cyber attacks against manufacturers.

But as manufacturers moved from air-gapped industrial systems to cloud-connectedsystems as part of the IT/OT convergence – using unpartitioned networks and insufficient access controls for proliferating IIoT devices – they created a massive, vulnerable attack surface, according to the Vectra report.

While air-gapped systems such as industrial controls have no connections by design to guard against malicious tampering, IT/OT convergence has connected these systems to information technologynetworks with little accounting for security vulnerabilities.

Many factories connect IIoT devices to flat, unpartitioned networks that rely on communication with general computing devices and enterprise applications. Since IIoT devices support few if any native cybersecurity measures, connecting them to easily infected applications, computers and unsegregated IP networks only invites trouble.

In the past, manufacturers relied on more customized, proprietary protocols, which made mounting an attack more difficult for cybercriminals. The conversion from proprietary protocols to standard protocols makes it easier to infiltrate networks to spy, spread and steal.

Few if any cyberattackers know and understand the proprietary protocols those closed legacy systems used. But it’s easy for most criminal hackers and their exploits to access standard IP network protocols just as WannaCry abuses the SMB protocol where there is no patch.

Real-time network visibility is crucial 

Industry 4.0 brings with it a new operational risk for connected, smart manufacturers and digital supply networks. The interconnected nature of Industry 4.0-driven operations and the pace of digital transformation mean that cyber attacks can have far more damaging effects than ever before, and manufacturers and their supply networks may not be preparedfor the risks.

Wherever cyber attacks interfere business continuity for business and information processes, they can also disrupt operational technologies that render products and get them out the door.

For cyber-risk to be adequately addressedin the age of Industry 4.0, manufacturing organizations need to ensure that proper visibility and response capabilities are in place to detect and respond to events as they occur. As in the case of the TSMC ransomware debacle, anything less than real-time detection and response is too little, too late to avoid production downtime.

There is no visibility into these systems to enable real-time detection before cyber attacks spread. Visibility into these internal connected systems is necessary to curtail the extent of damage from a cyberattack.

Manufacturing security operations now require automated, real-time analysis of entire networks to proactively detect and respond to in-progress threats before they do damage.

The Vectra 2018 Spotlight Report on Manufacturing

The 2018 Spotlight Report on Manufacturing delineates the many attack types and behaviors that the Cognito platform captured. The Cognito threat-detection and hunting platform monitored traffic and collected rich metadata from more than 4million devices and workloads from customer cloud, data center, and enterprise environmentsto reveal the cyberattacker behaviors.

Cyber attacks on manufacturers increased in severity from January to June 2018 based on data that the Vectra Cognito platform collected. The Vectra report confirms that all manufacturing industries are at equal risk of cyberattacks.

To learn about other findings pertinent to your Industry 4.0 cybersecurity risk, download the 2018 Spotlight Report on Manufacturing.

Christopher Morales is the head of security analytics at Vectra, a San Jose, Calif. cybersecurity firm that detects hidden cyberattacks and helps threat hunters improve the efficiency of incident investigations.

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North American semiconductor equipment industry posts July 2018 billings

North America-based manufacturers of semiconductor equipment posted $2.36 billion in billings worldwide in July 2018 (three-month average basis), according to the July Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 4.9 percent lower than the final June 2018 level of $2.48 billion, and is 4.1 percent higher than the July 2017 billings level of $2.27 billion.

“Global billings declined for the second month in a row, indicative of customer push-outs,” said Ajit Manocha, president and CEO of SEMI. “We expect the industry to weather this soft patch and end the year overall with strong growth.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.

Billings
(3-mo. avg.)
Year-Over-Year
February 2018
$2,417.8
22.5%
March 2018
$2,431.8
16.9%
April 2018
$2,689.9
25.9%
May 2018
$2,702.3
8.1%
June 2018 (final)
$2,484.3
8.0%
July 2018 (prelim)
$2,363.1
4.1%

Source: SEMI (www.semi.org), August 2018

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

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Helping the microchip industry go (very low) with the flow

A new study by scientists at the National Institute of Standards and Technology (NIST) has uncovered a source of error in an industry-standard calibration method that could lead microchip manufacturers to lose a million dollars or more in a single fabrication run. The problem is expected to become progressively more acute as chipmakers pack ever more features into ever smaller space.

The error occurs when measuring very small flows of exotic gas mixtures. Small gas flows occur during chemical vapor deposition (CVD), a process that occurs inside a vacuum chamber when ultra-rarefied gases flow across a silicon wafer to deposit a solid film. CVD is widely used to fabricate many kinds of high-performance microchips containing as many as several billion transistors. CVD builds up complex 3D structures by depositing successive layers of atoms or molecules; some layers are only a few atoms thick. A complementary process called plasma etching also uses small flows of exotic gases to produce tiny features on the surface of semiconducting materials by removing small amounts of silicon.

The exact amount of gas injected into the chamber is critically important to these processes and is regulated by a device called a mass flow controller (MFC). MFCs must be highly accurate to ensure that the deposited layers have the required dimensions. The potential impact is large because chips with incorrect layer depths must be discarded.

“Flow inaccuracies cause nonuniformities in critical features in wafers, directly causing yield reduction,” said Mohamed Saleem, Chief Technology Officer at Brooks Instrument, a U.S. company that manufactures MFCs among other precision measurement devices. “Factoring in the cost of running cleanrooms, the loss on a batch of wafers scrapped due to flow irregularities can run around $500,000 to $1,000,000. Add to that cost the process tool downtime required for troubleshooting, and it becomes prohibitively expensive.”

Modern nanofabrication facilities cost several billion dollars each, and it is generally not cost-effective for a company to constantly fine tune CVD and plasma etching. Instead, the facilities rely on accurate gas flows controlled by MFCs. Typically, MFCs are calibrated using the “rate of rise” (RoR) method, which makes a series of pressure and temperature measurements over time as gas fills a collection tank through the MFC.

“Concerns about the accuracy of that technique came to our attention recently when a major manufacturer of chip-fabrication equipment found that they were getting inconsistent results for flow rate from their instruments when they were calibrated on different RoR systems,” said John Wright of NIST’s Fluid Metrology Group, whose members conducted the error analysis.

Wright was particularly interested because for many years he had seen that RoR readings didn’t agree with results obtained with NIST’s “gold standard” pressure/volume/temperature/time system. He and colleagues developed a mathematical model of the RoR process and conducted detailed experiments. The conclusion: conventional RoR flow measurements can have significant errors because of erroneous temperature values. “The gas is heated by flow work as it is compressed in the collection tank, but that is not easily accounted for: it is difficult to measure the temperature of nearly stationary gas.”

Wright and colleagues found that without corrections for these temperature errors, RoR readings can be off by as much as 1 percent, and perhaps considerably more. That might not seem like a lot, but low uncertainty is critical to attaining uniformity and quality in the chip manufacturing process. And the challenge is growing. Current low-end flow rates in the semiconductor industry are in the range of one standard cubic centimeter (1 sccm)–about the volume of a sugar cube–per minute, but they will soon shrink by a factor of 10 to 0.1 sccm.

Precise flow measurement is a particularly serious concern for manufacturing processes that use etching of deposited layers to form trench-like features. In that case, the MFC is often open for no more than a few seconds.

“A tiny amount of variation in the flow rate has a profound effect on the etch rate and critical dimensions of the structures” in very large-scale integrated circuits, said Iqbal Shareef of Lam Research, a company headquartered in California that provides precision fabrication equipment to microchip manufacturers.

“So, we are extremely concerned about flow rates being accurate and consistent from chamber to chamber and wafer to wafer,” Shareef said. “Our industry is already headed toward very small flow rates.”

“We are talking about wafer uniformity today on the nanometer and even subnanometer scale,” Shareef said.

That’s very small. But it’s what the complexity of three-dimensional chip manufacturing increasingly demands. Not so long ago, “a 3D integrated circuit used to have four layers of metals,” said William White, Director of Advanced Technology at HORIBA Instruments Incorporated, a global firm that provides analytical and measurement systems. “Now companies are regularly going to 32 layers and sometimes to 64. Just this year I heard about 128.” And some of those chips have as many as 3,000 process steps.

“Each 300 mm wafer can cost up to $400, and contains 281 dies for a die size of 250 to 300 mm2,” Brooks’ Saleem said. “Each die in today’s high-end integrated circuits consists of about three to four billion transistors. Each wafer goes through 1 or 2 months of processing that includes multiple runs of separate individual processes,” including chemical vapor deposition, etch, lithography and ion implantation. All those processes use expensive chemicals and gases.

Many companies are already re-examining their practices in light of the NIST publication, which provides needed theoretical explanations for the source of RoR flow measurement errors. The theory guides designers of RoR collection tanks and demonstrates easy-to-apply correction methods. RoR theory shows that different temperature errors will occur for the different gases used in CVD processes. The NIST publication also provides a model uncertainty analysis that others can use to know what level of agreement to expect between MFCs calibrated on different RoR systems.

“NIST serves as a reliable reference for knowledge and measurement where industry can assess agreement between their systems,” Wright said. “As manufacturers’ measurement needs push to ever lower flows, so will NIST calibration standards.”

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The largest compound semiconductor device maker in China selects ClassOne Solstice CopperMax electroplating system

ClassOne Technology, a supplier of new electroplating and wet process tools to the 200mm and smaller semiconductor manufacturing industry, today announced a multi-tool sale of its flagship Solstice® CopperMax™ electroplating system to China’s premier compound semiconductor manufacturer. As the largest such supplier in China—among the largest Gallium Arsenide (GaAs) fabs in the world—ClassOne’s new client will use CopperMax™ to anchor the production of highly-advanced power chips with breakthrough designs suitable for a variety of leading-edge semiconductor markets.

“ClassOne has emerged as the supplier of choice for the exacting requirements of the Compound Semiconductor industry,” says ClassOne CEO Byron Exarcos. “ClassOne has presence in each of the leading Compound Semiconductor fabs around the world, now including a global leader in the development and manufacture of semiconductors based on GaAs substrates. This sale further confirms ClassOne’s leadership status in electroplating technology worldwide.”

ClassOne expects multiple similar sales in the coming months, as semiconductor manufacturing facilities throughout Asia expand their processing capabilities for advanced applications such as 3D Sensing, Autonomous Vehicles, and 4G/5G Communications—applications that require highly-advanced Compound Semiconductor chip technology.

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Worldwide semiconductor revenue hit record $120.8B in Q2 2018

Global semiconductor industry revenue grew 4.4 percent, quarter over quarter, in the second quarter of 2018, reaching a record $120.8 billion. Semiconductor growth occurred in all application markets and world regions, according to IHS Markit (Nasdaq: INFO).

“The explosive growth in enterprise and storage drove the market to new heights in the second quarter,” said Ron Ellwanger, senior analyst and component landscape tool manager, IHS Markit. “This growth contributed to record application revenue in data processing and wired communication markets as well as in the microcomponent and memory categories.”

Due to the ongoing growth in the enterprise and storage markets, sequential microcomponent sales grew 6.5 percent in the second quarter, while memory semiconductor revenue increased 6.4 percent. “Broadcom Limited experienced exceptional growth in its wired communication division, due to increased cloud and data-center demand,” Ellwanger said.

Memory component revenue continued to rise in the second quarter, compared to the previous quarter, reaching $42.0 billion dollars. “This is the ninth consecutive quarter of rising revenue from memory components, and growth in the second quarter of 2018 was driven by higher density in enterprise and storage,” Ellwanger said. “This latest uptick comes at a time of softening prices for NAND flash memory. However, more attractive pricing for NAND memory is pushing SSD demand and revenue higher.”

Semiconductor market share

Samsung Electronics continued to lead the overall semiconductor industry in the second quarter with 15.9 percent of the market, followed by Intel at 13.9 percent and SK Hynix at 7.9 percent. Quarter-over-quarter market shares were relatively flat, with no change in the top-three ranking. SK Hynix achieved the highest growth rate and record quarterly sales among the top three companies, recording 16.4 percent growth in the second quarter.

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Sanan IC goes global, emerges as a world-class III-V technology platform company

Sanan Integrated Circuit Co., a pure-play compound semiconductor foundry, today announces its entry into the North American, European, and Asia Pacific (APAC) markets with their advanced III-V technology platform. With their broad portfolio of gallium arsenide (GaAs) HBT, pHEMT, BiHEMT, integrated passive device (IPD), filters, gallium nitride (GaN) power HEMT, silicon carbide (SiC), and indium phosphide (InP) DHBT process technologies, they cover a wide range of applications among today’s active microelectronics and photonics markets. Sanan IC is strongly focused on high performance, large scale, and high quality III-V semiconductor manufacturing and on serving the RF, millimeter wave, power electronics, and optical markets.

Founded in 2014, headquartered in Xiamen City, in the Fujian province of south China, Sanan IC is subsidiary of Sanan Optoelectronics Co., Ltd., the leading LED chip manufacturing company, based on GaN and GaAs technologies. Leveraging high volume production and years of investment in numerous epitaxial wafer reactors of its parent company for the LED lighting and solar photovoltaic markets, Sanan IC is expanding their go-to-market strategy beyond the Greater China region as their process technologies and patent portfolio mature, with a vision to fulfill the needs of independent design manufacturers (IDM’s) and fabless design houses for high volume compound semiconductor fabrication.

“We see tremendous opportunity in serving the world-wide demand for large scale production of 6-inch III-V epitaxial wafers, driven by continual growth of the RF, millimeter wave, power electronics, and optical markets,” said Raymond Cai, Chief Executive Officer of Sanan IC. “Our vertically integrated manufacturing services over our broad compound semiconductor technology platform, with in-house epitaxy and substrate capabilities, make us an ideal foundry partner. Given the capital investments made on state-of-the art equipment and facilities, with full support from our parent company, Sanan Optoelectronics, combined with strategic partnerships, and a world-class team of scientists and technologists, Sanan IC is well positioned for success in this active compound semiconductor market”.

As cellular mobility and wireless connectivity proliferates in the Internet-of-Things (IoT), and 5G sub-6GHz evolves into millimeter wave, III-V technologies become even more critical to support the infrastructure and client device deployments by carriers worldwide. According to Yole Développement (Yole), a leading technology market research firm, part of Yole Group of Companies, the GaAs wafer market, comprised of RF, photonics, photovoltaics, and LEDs, is expected to grow to over 4 million units in 2023, with photonics having the highest growth at 37% CAGR1. GaN and SiC for power electronics, such as for data centers, electric vehicles (EVs), battery chargers, power supplies, LiDAR, and audio, are predicted to ramp up, with GaN reaching up to $460M shipments by 2022 with a CAGR of 79%2 while SiC projects to reach $1.4B at 29% CAGR by 20233. Optical components continue to be in high demand for datacom, telecom, consumer, automotive and industrial markets, leading to increased revenues for photodectors, laser diodes, and especially VCSELs with expected shipments of $3.5B in 20234. As these applications emerge, Sanan IC is poised to support the industry’s needs.

Sources:
1GaAs Wafer & Epiwafer Market: RF, Photonics, LED & PV Applications Report, Yole Développement (Yole), 2018
2,3Power SiC 2018: Materials, Devices and Applications Report, Yole Développement (Yole), 2018
4Source: VCSELs – Technology, Industry & Market Trends report, Yole Développement (Yole), 2018

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ASIC Design Services adds Core Deep Learning IP to SiFive DesignShare program

SiFive, a provider of commercial RISC-V processor IP, today announced that ASIC Design Services, a design house, IP provider, and a distributor for FPGA and EDA software, has joined the DesignShare ecosystem. Through this partnership, ASIC Design Services will provide its Core Deep Learning (CDL) technology that accelerates Convolutional Neural Networks (CNNs) on power-constrained embedded hardware platforms.

ASIC Design Services’ CDL technology optimizes its CNN accelerator FPGA core for performance, logic resources, and low power – making CDL suitable for IoT edge and node applications. The CDL Coldbrew software stack performs quantization and compression of CNNs, design space exploration, and generates a solution optimized for performance, resources, and low power. Coldbrew is built on the Caffe deep learning framework, and provides a simple user interface to bridge the gap between high-level CNN specification and FPGA design.

“We are excited about the increased performance and energy efficiency offered by FPGAs,” said Tony Dal Maso, CEO of ASIC Design Services. “Today, we can achieve 100 Gops/s/Watt on a low-power FPGA solution. By partnering with SiFive we enable the global community of embedded designers to accelerate deep learning solutions on embedded platforms.”

The availability of ASIC Design Services’ CDL IP through the DesignShare program shortens the time to market and removes common barriers to entry that have traditionally prevented smaller companies from developing custom silicon. Companies like SiFive, ASIC Design Services and other DesignShare partners provide low- or no-cost IP to emerging companies, minimizing the upfront engineering costs needed to bring a custom chip from design to realization.

“Adding artificial intelligence and neural networks to edge devices is increasingly in demand,” said Shafy Eltoukhy, vice president of operations and head of DesignShare for SiFive. “With ASIC Design Services addition to the DesignShare ecosystem, we continue to expand the range of IP available to designers looking to bring prototype devices to life.”

Since DesignShare launched in 2017, the program has grown to include a wide range of IP solutions, from complete ASIC solutions and trace technology to embedded memory and precision PLL. For more information on DesignShare and to see the complete list of available technologies, visit www.sifive.com/designshare.

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TowerJazz to showcase SiGe and silicon photonic process solutions for 100 to 400Gb/s optical data links at ECOC

TowerJazz, the global specialty foundry, today announced its participation at the 44th European Conference on Optical Communication (ECOC) being held in Rome, Italy on September 23-27, 2018. The Company will showcase its advanced SiGe (Silicon Germanium) process, with speeds in excess of 300GHz, and its newest production SiPho (Silicon Photonics) process built into data center high-speed optical data links.

TowerJazz has a significant foundry share of the 100Gb/s transceiver market served by its SiGe Terabit Platform and will showcase even higher SiGe transistor speeds and patented features appropriate for 200 and 400Gb/s communication ICs such as  transimpedance amplifiers (TIAs), laser and modulator drivers, and clock and data recovery circuits.

TowerJazz’s SiPho production platform enables high bandwidth photo diodes, together with waveguides and modulators, with a roadmap to allow InP components on the same die and permit a high-level of optical integration for next-generation data center optical links.  An open design kit is available to all customers and supported by prototyping and shuttle runs.

To set up a meeting or see a demo with TowerJazz technical experts at the TowerJazz ECOC booth (#569), or for more information, please click here or inquire at: info@towerjazz.com.

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Soitec and MBDA to acquire Dolphin Integration Assets

Soitec (Euronext Paris), a designer and manufacturer of semiconductor materials, and MBDA, announce the joint acquisition of Dolphin Integration.

Dolphin Integration is an industry recognized provider of semiconductor design, silicon IP and SoC (System-On-Chip) solutions for low power applications. Headquartered in Grenoble, Dolphin Integration was founded in 1985. It currently employs 155 people, including 130 design engineers. For the fiscal year ended March 31th, 2018, the company generated revenues of 17 million Euros.

The joint venture formed by Soitec and MBDA acquires Dolphin Integration, including all employees. The resulting ownership of the joint venture is as follows: Soitec at 60% and MBDA at 40%.

The transaction was authorized today by the Commercial Court of Grenoble. It comes as a prompt and positive outcome of Dolphin Integration insolvency proceedings. The company went into receivership on July 24, 2018.

Soitec and MBDA each provide complementary strategic support to Dolphin Integration.

Soitec brings its engineered substrates expertise and unique low-power design methodology (body biasing) to accelerate Dolphin Integration design activities in low-power electronic devices, where a growing number of critical chips are built on FD-SOI technology. In addition, Soitec will strengthen Dolphin Integration’s position within the entire semiconductor ecosystem, to develop and promote products and services in several strategic markets, including mobile devices and infrastructure, data centers, and space and industrial applications.

MBDA, a strategic customer of Dolphin Integration for defense applications since 2004, strengthens its existing industrial collaboration and long-term commercial pipeline for ASIC (Application Specific Integrated Circuit) and SoC (System on Chip) products. With the support of MBDA, Dolphin Integration will be able to advance its positions in aerospace and defense design.

Soitec and MBDA confident in Dolphin Integration profitable growth.

Soitec and MBDA together committed to a financial investment of around 6 million Euros including the acquisition of most of Dolphin Integration’s assets, the payment of certain liabilities and a significant cash injection to finance Dolphin Integration’s working capital requirements.

Soitec and MBDA are confident in their ability to turnaround the financial position of Dolphin Integration. Dolphin Integration is expected to be fully consolidated into Soitec’s financial statements as of September 2018.

“Dolphin Integration represents a strategic opportunity for Soitec to reinforce a full IP and service offering related to energy efficient solutions for chip design on FD-SOI. This is a major differentiating factor for FD-SOI and a key accelerator of FD-SOI adoption in major market segments,” highlighted Paul Boudre, CEO of Soitec.

“MBDA investment will strengthen the French defense industrial base since it will provide Dolphin Integration with a more stable flow of defense related revenues and a closer technological collaboration that will allow it to enhance the access of its specialized microelectronics offering to the entire French and European defense industry,” said Antoine Bouvier, CEO of MBDA.

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Vacuum pump market growing at 6%. CAGR to cross $6.5B by 2024

In the last few years, biggies in the Vacuum Pump Market have set different business goals to attain a dominant market position. Their approach toward improving their current stance has been remarkably influencing the quality and design performance of vacuum pumps, which has positively impacted the shelf life and cost-effectiveness of the products. The optimized approach of players toward new product developments and business expansions is certainly poised to push vacuum pump market size. Some of the recent instances witnessed across vacuum pump market that are likely to etch a positive growth path for this industry are described below.

How Leybold, Atlas Copco, and Edwards combinedly contributed toward vacuum pump market expansion

Of late, it has been observed that reliability and cleanliness are becoming highly important in most of the production processes. Having recognized that efficient vacuum technology development could fulfill these industrial requirements, a few days before, Leybold, a subsidiary of the Atlas Copco Group, unveiled an oil-free vacuum pump with two variants of speed, which are designed to be useful in dusty and moist processes. Through in-depth R&D, the product manufacturers have successfully reduced the operating noise and maintenance cost associated with the Oil-Free VARODRY Vacuum Pump. In addition, the compact design helps users to integrate this product into existing systems very easily.

Speaking more about this product launch, the speed variants have made it ideal for industrial vacuum requirement with low investment and operating costs. This innovative product prevents oil leaks and particle emissions in a vacuum chamber, which will turn out to be a tremendous help to speed up industrial processes. It is thus rather overt, that with the launch of this maintenance-free and robust pump, Leybold has set a new benchmark ahead for the giants in vacuum pump market.

Prior to this launch, the parent company of Leybold, Atlas Copco unveiled its new product – a multiple dry claw vacuum pump system which is ideally suited for the industries operating in dry and hot working environments. This newly developed vacuum pump aims to provide high energy efficiency and better operational performance. The future deployment of this product for performing numerous dry pumping applications comprising pneumatic pumping, packaging lines, and drying processes is certain to fuel vacuum pump market trends over the years ahead.

With the development of a next-generation oil sealed rotary vane vacuum pump, the UK headquartered vacuum engineering company, Edwards had aimed to expand its customer base. This subsidiary of Atlas Copco designed a safe, stable, and compact size vacuum pump which could be suitable for applications in explosive environments especially in chemical processing industries. While developing this variant of vacuum pump, the designers of Edwards focused on customary requirements mainly across the U.S. and European belts. Post the launch, analysts deem that this approach could help Edwards considerably extend its customer base across North America and Europe. In addition, the deployment of these new products across the chemical, automotive, degassing, and pharmaceutical sectors has helped giants in vacuum pump market to extend their application scope across most of the industries.

It is rather overt that with the launch of a novel pumping system portfolio, core companies are looking forward to achieving competitive benefits ahead. The increasing need of highly efficient and environment-friendly pumping systems is considerably encouraging giants in vacuum pump market to carry out intensive research programs as well. The recent R&D outcomes such as improved lifecycle and cost-effectiveness will prove to be game-changing for the biggies in vacuum pump market, which is predicted to generate a revenue of over USD 6.5 billion by the end of 2025.

  • Key Industry participants for Vacuum Pump Market are –
  • Atlas Copco
  • Pfeiffer Vacuum Technology AG
  • Gardner Denver
  • Agilent Technologies Inc.
  • ULVAC Inc.
  • Ebara Corporation
  • Leybold GmbH
  • Busch Vacuum Pumps and Systems
  • Shimadzu Corporation
  • Kashiyama Industries Ltd.
  • KNF Neuberger GmbH
  • Gast Manufacturing Inc.
  • Becker GmbH
  • DEKKER Vacuum Technologies, Inc.
  • PPI Pumps Pvt. Ltd.

Powered by a widespread application scope and ongoing technological advancements, vacuum pump market trends have undergone a tremendous transformation since the last few years. The extensive involvement of industry players in research and development activities has been paving the way for remarkable breakthroughs in futuristic vacuum technology requirements. Having recognized the significance of frequent product launchesvacuum pump market contenders have been focusing lately on the development of customized solutions to strengthen their customer base.

Speaking of advancements in vacuum technology, the end-users across myriad sectors ranging from solar manufacturing to scientific instrumentation and flat panel display to semiconductors have been going the whole hog to tap the benefits of modern vacuum mechanisms. The subsequent deployment of modern vacuum pumps for pumping services across numerous industrial applications is thus poised to boost vacuum pump market share.

Browse key industry insights report, “Vacuum Pump Market Size By Lubrication (Dry, Wet), By Technology (Gas Capture/Binding Pumps, Gas Transfer Pumps [Positive Displacement Pumps, Kinetic Pumps]), By Product (Low Vacuum, Medium Vacuum, High Vacuum), By End-user (Chemical & Pharmaceutical, Semiconductor & Electronics, Oil & Gas, Food & Beverages, Wood, Paper & Pulp), Industry Analysis Report, Regional Outlook (U.S., Canada, Germany, UK, France, Spain, Italy, Russia, China, India, Japan, Australia, Indonesia, Malaysia, South Korea, Brazil, Mexico, South Africa, Saudi Arabia, UAE, Kuwait), Application Growth Potential, Price Trends, Competitive Market Share & Forecast, 2018 – 2025

https://www.gminsights.com/industry-analysis/vacuum-pump-market

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SiFive announces first open-source RISC-V-based SoC platform with NVIDIA Deep Learning Accelerator technology

SiFive, a provider of commercial RISC-V processor IP, today announced the first open-source RISC-V-based SoC platform for edge inference applications based on NVIDIA’s Deep Learning Accelerator (NVDLA) technology.

The demo will be shown this week at the Hot Chips conference and consists of NVDLA running on an FPGA connected via ChipLink to SiFive’s HiFive Unleashed board powered by the Freedom U540, the world’s first Linux-capable RISC-V processor. The complete SiFive implementation is well suited for intelligence at the edge, where high-performance with improved power and area profiles are crucial. SiFive’s silicon design capabilities and innovative business model enables a simplified path to building custom silicon on the RISC-V architecture with NVDLA.

NVIDIA open-sourced its leading deep learning accelerator over a year ago to spark the creation of more AI silicon solutions. Open-source architectures such as NVDLA and RISC-V are essential building blocks of innovation for Big Data and AI solutions.

“It is great to see open-source collaborations, where leading technologies such as NVDLA can make the way for more custom silicon to enhance the applications that require inference engines and accelerators,” said Yunsup Lee, co-founder and CTO, SiFive. “This is exactly how companies can extend the reach of their platforms.”

“NVIDIA open sourced its NVDLA architecture to drive the adoption of AI,” said Deepu Talla, vice president and general manager of Autonomous Machines at NVIDIA. “Our collaboration with SiFive enables customized AI silicon solutions for emerging applications and markets where the combination of RISC-V and NVDLA will be very attractive.”

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Seven top 15 semi suppliers of the first half of 2018 register ≥20% gains

IC Insights released its August Update to the 2018 McClean Report earlier this month.  This Update included a discussion of the top-25 semiconductor suppliers in 1H18 (the top-15 1H18 semiconductor suppliers are covered in this research bulletin) and Part 1 of an extensive analysis of the IC foundry market and its suppliers.

The top-15 worldwide semiconductor (IC and O-S-D—optoelectronic, sensor, and discrete) sales ranking for 1H18 is shown in Figure 1.  It includes seven suppliers headquartered in the U.S., three in Europe, two each in South Korea and Taiwan, and one in Japan.  After announcing in early April 2018 that it had successfully moved its headquarters location from Singapore to the U.S. IC Insights now classifies Broadcom as a U.S. company.

Figure 1

As shown, all but four of the top 15 companies had double-digit year-over-year growth in 1H18. Moreover, seven companies had ≥20% growth, including the five big memory suppliers (Samsung, SK Hynix, Micron, Toshiba/Toshiba Memory, and Western Digital/SanDisk) as well as Nvidia and ST.

The top-15 ranking includes one pure-play foundry (TSMC) and four fabless companies. If TSMC were excluded from the top-15 ranking, U.S.-based Apple would have been ranked in the 15th position. Apple is an anomaly in the top company ranking with regards to major semiconductor suppliers. The company designs and uses its processors only in its own products—there are no sales of the company’s MPUs to other system makers. IC Insights estimates that Apple’s custom ARM-based SoC processors and other custom devices had a “sales value” of $3.5 billion in 1H18.

IC Insights includes foundries in the top-15 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted. With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers. Foundries and fabless companies are identified in the Figure. In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

Overall, the top-15 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

In May 2018, Toshiba completed the $18.0 billion sale of its memory IC business to the Bain Capital-led consortium. Toshiba then repurchased a 40.2% share of the business. The Bain consortium goes by the name of BCPE Pangea and the group owns 49.9% of Toshiba Memory Corporation (TMC). Hoya Corp. owns the remaining 9.9% of TMC’s shares. The new owners have plans for an IPO within three years. Bain has said it plans to support the business in pursing M&A targets, including potentially large deals.

As a result of the sale of Toshiba’s memory business, the 2Q18 sales results shown in Figure 1 include the combined sales of the remaining semiconductor products at Toshiba (e.g., Discrete devices and System LSIs) and the new Toshiba Memory’s NAND flash sales. The estimated breakdown of these sales in 2Q18 is shown below:

Toshiba System LSI: $468M
Toshiba Discrete: $315M
Toshiba Memory Corporation: $3,107M
Total Toshiba/Toshiba Memory Corporation 2Q18 Sales: $3,890M

In total, the top-15 semiconductor companies’ sales surged by 24% in 1H18 compared to 1H17, four points higher than the total worldwide semiconductor industry 1H18/1H17 increase of 20%. Amazingly, the Big 3 memory suppliers—Samsung, SK Hynix, and Micron, each registered greater than 35% year-over-year growth in 1H18. Fourteen of the top-15 companies had sales of at least $4.0 billion in 1H18, three companies more than in 1H17. As shown, it took just over $3.7 billion in sales just to make it into the 1H18 top-15 semiconductor supplier list.

Intel was the number one ranked semiconductor supplier in 1Q17 but lost its lead spot to Samsung in 2Q17 as well as in the full-year 2017 ranking, a position it had held since 1993. With the continuation of the strong surge in the DRAM and NAND flash markets over the past year, Samsung went from having only 1% more total semiconductor sales than Intel in 1H17 to having 22% more semiconductor sales than Intel in 1H18!

It is interesting to note that memory devices are forecast to represent 84% of Samsung’s semiconductor sales in 2018, up three points from 81% in 2017 and up 13 points from 71% just two years earlier in 2016. Moreover, the company’s non-memory sales in 2018 are expected to be only $13.5 billion, up 8% from 2017’s non-memory sales level of $12.5 billion. In contrast, Samsung’s memory sales are forecast to be up 31% this year and reach $70.0 billion.

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Increase Reliability and Efficiency in Power Converter Designs

Tips for better power conversion.

Efficiently create and debug power converter designs using wide-bandgap power devices for vehicle electrification and HEMS applications to maximize their full potential. Learn more by reading Keysight’s three-part application note series, Increasing Reliability and Efficiency in Next Generation Power Converter Designs:

  • Part 1 – Power Device and Component Evaluation
  • Part 2 – Design Software Simulation
  • Part 3 – Hardware Design and Debug

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2018 IEEE IEDM to showcase breakthrough in semiconductor technology

The 64thannual IEEE International Electron Devices Meeting (IEDM), the world’s largest, most influential forum for technologists to unveil breakthroughs and new concepts in transistors and related micro/nanoelectronics devices, will be held December 1-5, 2018 at the Hilton San Francisco Union Square hotel. The late-news submission deadline is September 10.

The IEDM’s tradition of spotlighting more leading work in more areas of the field continues, even as the conference evolves to support the interdisciplinary and continuing educational needs of the scientists, engineers and students whose efforts make possible the expansion of the worldwide electronics industry.

“We live in a time when electronics technology touches more aspects of business and industry than ever before,” said Kirsten Moselund, IEDM 2018 Publicity Chair and Research Staff Member at IBM Research–Zurich. “No matter what their specialty is, attendees will come away from the conference with a deeper understanding of the challenges and opportunities before them.”

“In terms of industrial applications, the evening panel session on EUV will give attendees the opportunity to explore and debate this emerging technology with the very people who are driving it forward,” said Rihito Kuroda, IEDM 2018 Publicity Vice Chair and Associate Professor at Tohoku University. “This is just one way in which the IEDM conference gives people insights into the technologies that will become mainstream in a few years.”

Here are details of some of the talks and events that will take place at this year’s IEDM. The papers to be presented in the technical sessions will be chosen in late September and highlights from them will be forthcoming soon thereafter:

Focus Sessions

  • Quantum Computing – Quantum computing will enable new types of algorithms to tackle problems in areas from materials science to medicine to artificial intelligence. We are still in early stages, facing fundamental questions such as: What is the best way to implement a quantum bit of information? How to connect them together? How to scale to larger systems without being overwhelmed by errors? This session brings together experts at the forefront of quantum computing research. Starting from an applications perspective, attendees will hear about different approaches to address fundamental questions at the device level; the progress achieved so far; and next steps.
    • Application Requirements for Quantum Computing, John Preskill, Caltech
    • Materials and Device Challenges for Near-Term Superconducting Quantum Processors, Jerry Chow, IBM
    • Towards Scalable Silicon Quantum Computing, Maud Vinet, CEA-Leti
    • Silicon Isotope Technology for Quantum Computing, Kohei Itoh, Keio University
    • Qubit Device Integration Using Advanced Semiconductor Manufacturing Process Technology, Ravi Pillarrisetty, Intel
    • Scalable Quantum Computing with Single Dopant Atoms in Silicon, Andrea Morello, Univ. New South Wales
    • Majorana Qubits, Leo Kouwenhoeven, Microsoft
  • Future Technologies Towards Wireless Communications: 5G and Beyond– 5G technology will drastically reduce limitations on accessibility, bandwidth, performance, and latency, but as it triggers fundamentally new applications it also will impose unique hardware requirements. This focus session will set a big picture view and then narrow down to how innovations in CMOS technologies, devices, filters, transceivers and antennas are coming together to enable the 5G platform.
    • Intel 22nm FinFET (22FFL) Process Technology for RF and mmWave Applications and Circuit Design Optimization for FinFET Technology, Hyung-Jin Lee, Intel
    • RFIC/CMOS Technologies for 5G, mmWave and Beyond, Ali Niknejad, UC Berkeley
    • GaN HEMTs for 5G Base Station Applications, Shigeru Nakajima, Sumitomo Electron Devices
    • Highly Integrated mm-Wave Transceivers for Communication Systems,Vadim Issakov, Infineon
    • BAW Filters for 5G Bands, Robert Aigner, Qorvo
    • Reconfigurable Micro/Millimeter-wave Filters, Dimitrios Peroulis, Purdue
  • Challenges for Wide Bandgap Device Adoption in Power Electronics– Wide bandgap (WBG) power devices offer potential savings in both energy and cost. But converters powered by WBG devices require innovation at all levels, entailing changes to system design, circuit architecture, qualification metrics and even market models. Can SiC or GaN push beyond what silicon can possibly achieve? What are the big challenges researchers should answer over the next decade? A team of experts will interpret the landscape and discuss challenges to the widespread adoption of these technologies.
    • GaN and SiC Devices for Automotive Applications, Tetsu Kachi, Nagoya University
    • SiC MOSFET for Mainstream Adoption, Peter Friedrichs, Infineon
    • GaN Power Commercialization with Highest Quality-Highest Reliability 650V HEMTs- Requirements, Successes and Challenges, Primit Parikh, Transphorm
    • The Current Status and Future Prospects of SiC High Voltage Technology, Andrei Mihaila, ABB
    • Barriers to Wide Bandgap Semiconductor Device Adoption in Power Electronics, Isik Kizilyalli, ARPA-E
    • High to Ultra-High Voltage SiC Power Device Technology, Yoshiyuki Yonezawa, AIST
    • Effects of Basal Plane Dislocations on SiC Power Device Reliability, Robert E. Stahlbush, Naval Research Laboratory
  • Interconnects to Enable Continued Technology Scaling –BEOL copper (Cu) interconnects are close to end-of-life as a manufacturing technology, while the increasing complexity of MEOL processes requires novel materials. Also, the end of the Cu roadmap will coincide with significant changes in the dominant transistor architecture, and therefore the interaction between transistor architecture and interconnect will drive future interconnect development. This session provides a holistic perspective of interconnect scaling challenges and solutions. It will address the drivers of future interconnect architectures, the process options likely to be implemented in manufacturing, and how they will be tuned to ensure circuit reliability is maintained.
    • Interconnect Design and Technology Optimization for Conventional and Exotic Nanoscale Devices: A Physical Design Perspective, Naeemi, Georgia Tech
    • Mechanisms of Electromigration Damage in Cu Interconnects, K. Hu, IBM
    • Interconnect Metals Beyond Copper: Reliability Challenges and Opportunities, K. Croes, Imec
    • Microstructure Evolution and Effect on Resistivity for Cu Nano-interconnects and Beyond, Paul Ho, UT Austin
    • Integrating Graphene into Future Generations of BEOL Interconnects,-S. Philip Wong, Stanford
    • Interconnect Trends for Single Digit Nodes, Mehul Naik, Applied Materials

90-Minute Tutorials – Saturday, Dec. 1

A series of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, bridging the gap between textbook-level knowledge and leading-edge current research.

  • Reliability Challenges in Advanced Technologies,Ryan Lu, TSMC
  • STT-MRAM Design and Device Requirements, Shinichiro Shiratake, Toshiba Memory
  • Quantum Computing Primer, Mark B. Ritter, IBM
  • Power Transistors in Integrated BCD Technologies, Hal Edwards, Texas Instruments
  • Design-Technology Co-optimization at RF and mmWave, Bertand Parvais, IMEC
  • Emerging Device Technologies for Neuromorphic Computing, Damien Querlioz, CNRS

Short Courses – Sunday, Dec. 2

Full-day Short Courses will be held, offering the opportunity to learn about important areas and developments, and to network with experts from around the world.

  • It’s All About Memory, Not Logic!, organized by Nirmal Ramaswamy, Micron
  • DRAM: Its Challenging History and Future, Dong Soo Woo, Samsung
  • 3D Flash Memories: Overview of Cell Structures, Operations and Scaling Challenges, Makoto Fujiwara, Toshiba Memory Corporation.
  • Emerging Memories Including Cross-Point, Opportunities and Challenges, Kiran Pangal, Intel
  • Memory Reliability, Qualification and their Relation to System-Level Reliability Strategies, Todd Marquart, Micron
  • Packaging Technology for High Bandwidth Memory, Nick (Namseog) Kim, SK Hynix
  • Processing in Memory (PIM): Performance and Thermal Challenges and Opportunities, Mircea Stan, UVA
  • Scaling Survival Guide in the More-than-Moore Era, organized by Jin Cai, TSMC
  • Extreme-UV Lithography – Principles, Present Status and Outlook,Tony Yen, ASML
  • MOSFET Scaling Knobs (GAA, NCFET…) and Future Alternatives,Witek Maszara, Globalfoundries
  • Overcoming Variation Challenges, Sivakumar Mudanai, Intel
  • Embedded Memory: Present Status and Emerging Architecture and Technology for Future Applications,Eric Wang, TSMC
  • 3D Integration for Density and Functionality,Julien Ryckaert, Imec
  • Advanced Packaging: the Next Frontier for Moore’s “Law,” Subramanian Iyer, UCLA

Plenary Presentations – Monday, Dec. 3

  • Future Computing Hardware for AI, Jeffery Welser, Vice President, IBM Research-Almaden
  • 4th Industrial Revolution and Foundry: Challenges and Opportunities,” Eun Seung Jung, President of Foundry Business, Samsung Electronics
  • The Status, Challenges and Opportunities of 5G, Prof. Gerhard P. Fettweis, TU Dresden

Evening Panel Session – Tuesday evening, Dec. 4

  • EUV: Too Little, Too Late, Too Expensive or the Ultimate Cure-All?,organized by Sanjay Natarajan, Senior VP of Applied Materials. Much progress has been made in EUV patterning technology, and yet manufacturing throughput, masks, pellicles and resists still persist as problems today. The complexity of reliably transferring features at the 7nm node and below using quadruple patterning and 193nm immersion is affecting yield, affecting the cost-per-gate reduction and slowing down Moore’s Law. The industry eagerly awaits EUV, but is it too little, too late and too expensive, or is it the ultimate panacea? A team of world-renowned experts from the leading logic and memory IDMs, foundries and fabless companies will vigorously debate the issue.

Luncheon – Wednesday, Dec. 5

The speakers are yet to be determined, but IEDM will have a new lunch event this year that features industry leaders engaging the audience on the state of the industry, and on careers in device and VLSI technology.

Vendor Exhibition/Poster Sessions

  • A vendor exhibition will be held once again, with special exhibit events in the evenings.
  • This year two poster sessions will be held, one on MRAM technology organized by the IEEE Magnetics Society, the other a student research showcase hosted by the Semiconductor Research Corporation.

Further information about IEDM

For registration and other information, visit www.ieee-iedm.org.

Follow IEDM via social media

About IEEE
IEEE is the world’s largest technical professional organization dedicated to advancing technology for the benefit of humanity. Through its highly cited publications, conferences, technology standards, and professional and educational activities, IEEE is the trusted voice in a wide variety of areas ranging from aerospace systems, computers, and telecommunications to biomedical engineering, electric power, and consumer electronics. Learn more at http://www.ieee.org.

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Nordson SONOSCAN unveils Gen7 tool on Windows 10

Nordson SONOSCAN, a developer and producer of acoustic micro imaging (AMI) tools, announces its new Gen7™ laboratory style acoustic micro-imaging tool. The new Gen7 AMI tool enhances operator productivity and part throughput rate by providing greater versatility in transducer movement, faster scanning of samples, and faster processing of data.

Orders are now being taken for the Gen7 AMI tool, which, like its predecessors in the Nordson SONOSCANC-SAM® line, is designed for analytical work on small numbers of samples, although it can also screen modest quantities of components. Among its differentiating features:

  • 50% higher screening throughput from faster transducer motors.
  • Scan area significantly enlarged, so more parts can be scanned at one time.
  • Upward and downward range of Z movement of the transducer more than doubled to enable scanning of samples having a greater range of height variation.
  • Windows® 10 operating system and Sonolytics 2™ user interface have replaced Windows® 7 and Sonolytics™, respectively.
  • Intel’s i7 seventh generation chips make the system’s computer hardware 33% faster, giving, for example, quicker delivery of Digital Image Analysis.
  • Both monitors have high resolution 4K screens to reveal more detail.
  • Includes Waterplume™ technology, so a separate C-SAM tool is not needed to image IGBT modules.

Users will notice that frequently used menu items now appear in the User Interface, eliminating the need to open a menu. Other changes include easy access to the current timing mode in the A-Scan and the ability to Go To a TOF directly from the movement interface.

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RF power semiconductors for wireless infrastructure over $1B for 2018 with GaN grabbing more share

RF power semiconductors for wireless infrastructure (for <4GHz and >3W) was over a US$1 billion business for 2018. The segment was essentially revenue flat, but Gallium Nitride (GaN) continues to make inroads into this segment.

“Gallium Nitride should continue to gain share over the next few years,” noted ABI Research Director Lance Wilson. “It bridges the gap between two older technologies, exhibiting the high-frequency performance of Gallium Arsenide combined with the power handling capabilities of Silicon LDMOS. It is now a mainstream technology which has achieved measurable market share and, in the future, will capture a significant part of the market.”

The wireless infrastructure sub-segment while representing about two-thirds of total RF power device sales has been anemic recently but is still holding its own.

The eventual deployment of 5G also offers an upside for the wireless Infrastructure segment. The main issue is one of timing on a large-scale rollout. Wilson also added, “the business environment for the RF power semiconductor device business has become more complex with potential trade tariffs, merger and acquisition troubles and other similar issues clouding the market”.

These findings are from ABI Research’s RF Power Semiconductor Devices for Mobile Wireless Infrastructure report. These reports are part of the company’s 5G & Mobile Network Infrastructureresearch service, which includes research, data, and Executive Foresights.

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Adesto demonstrates resistive RAM technology targeting high-reliability applications

Adesto Technologies (NASDAQ:IOTS), a provider of application-specific semiconductors for the IoT era, announced it will present new research showing the significant potential for Resistive RAM (RRAM) technology in high-reliability applications such as automotive. Adesto Fellow Dr. John Jameson, who led the research team, will share the results at the ESSCIRC-ESSDERC 48th European Solid-State Device Research Conference, being held in Germany on September 4th, 2018.

RRAM has great potential to become a widely used, low-cost and simple embedded non-volatile memory (NVM), as it utilizes simple cell structures and materials which can be integrated into existing manufacturing flows with as little as one additional mask. However, many RRAM technologies to-date have faced integration and reliability challenges. Adesto’s engineers will describe recent innovations that significantly increase the reliability of Adesto’s RRAM technology (trademarked as CBRAM®), making it a promising candidate for high-reliability applications. CBRAM consumes less power, requires fewer processing steps, and operates at lower voltages as compared to conventional embedded flash technologies.

“We’re delighted to share our latest RRAM research with the prestigious technical community at ESSCIRC-ESSDERC,” said Dr. Venkatesh Gopinath, VP of CBRAM and RRAM Technology and Production Development at Adesto. “For the first time, RRAM is being demonstrated as an ideal low-cost, one-mask embedded NVM for high-reliability applications. Adesto was the first company to bring commercial RRAM devices to market, and now our CBRAM technology is production-proven for IoT and other ultra-low power applications. Our continued innovation and advancements will bring the benefits of CBRAM to an even broader range of applications.”

Dr. Jameson will present the Adesto research on Tuesday, September 4th at 15:00 local time.

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WFE semiconductor equipment billings to drop 24% in second half of 2018

On the heels of a 37.3% growth in wafer front end (WFE) semiconductor equipment growth in 2017, the market will grow only 10% in 2018 to $62.3 billion, according to the report “The Global Semiconductor Equipment: Markets, Market Shares, Market Forecasts,” recently published by The Information Network, (www.theinformationnet.com) a New Tripoli, PA-based market research company.

For the first six months of 2018, WFE billings were $35.3 billion, meaning billings of $27.0 billion will be registered in the second half of 2018 if the sector as a whole grows 10% in CY 2018.

This means a drop of 24% between 1H 2018 and 2H 2018.

The chart below shows that U.S. equipment companies held a 48.8% share of the total sector in 1H 2018 followed by Japan with a 30.3% share and ROW (primarily Europe) with a 26.9% share. For 2H 2018, the weak Japanese Yen means Japan will have a 29.1% share, but stronger EUV sales by ASML will mean Europe’s share will grow to 28.0%.

The memory market is moving into a period of oversupply: NAND oversupply started six months ago and has resulted in device price drops, while DRAMs will reach an oversupply situation in the next few months. As a result, market leader Samsung Electronics has pushed out purchases. Foundry leader TSMC has reduced its estimate for sales revenue growth in 2018 and its capital expenditure budget.

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IBM and Synopsys accelerate 3nm process development with DTCO innovations

Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration with IBM to apply design technology co-optimization (DTCO) to the pathfinding of new semiconductor process technologies for the 3-nanometer (nm) process node and beyond. DTCO is a methodology for efficiently evaluating and down-selecting new transistor architectures, materials and other process technology innovations using design metrics, starting with an early pathfinding phase before wafers become available. The collaboration will extend the current Synopsys DTCO tool flow to new transistor architectures and other technology options while enabling IBM to develop early process design kits (PDKs) for its partners to assess the power, performance, area, and cost (PPAC) benefits at IBM’s advanced nodes.

“Process technology development beyond 7 nanometers requires the exploration of new materials and transistor architectures to achieve optimum manufacturability, power, performance, area, and cost. A major challenge for foundries is to converge on the best architecture in a timely manner while vetting all the possible options,” said Dr. Mukesh Khare, vice president of Semiconductor Research, IBM Research Lab. “Our DTCO collaboration with Synopsys allows us to efficiently select the best transistor architecture and process options based on metrics derived from typical building blocks, such as CPU cores, thus contributing to faster process development at reduced cost.”

In this collaboration, IBM and Synopsys are developing and validating new patterning techniques with Proteus™ mask synthesis, modeling new materials with QuantumATK, optimizing new transistor architectures with Sentaurus™ TCAD and Process Explorer, and extracting compact models with Mystic. Design rules and process assumptions derived from these process innovations are used to design and characterize a standard cell library while Fusion Technology™ at the block level using the Synopsys physical implementation flow based on IC Compiler™ II place-and-route, StarRC™ extraction, SiliconSmart® characterization, PrimeTime® signoff, and IC Validator physical verification benefits the evaluation of PPAC.

The scope of the joint development agreement covers multiple facets, including:

  • DTCO to optimize transistor- and cell-level design across routability, power, timing, and area
  • Evaluate and optimize new transistor architectures, including gate-all-around nanowire and nanoslab devices, with process and device simulation
  • Optimize variation-aware models for SPICE simulation, parasitic extraction (PEX), library characterization, and static timing analysis (STA) to accurately encapsulate the effects of variation on timing and power for highest-reliability design with least over-design and design flow runtime overhead
  • Gather gate-level design metrics to refine the models, library architecture, and design flows to maximize PPAC benefits

“Synopsys has developed the only complete DTCO solution, from materials exploration to block-level physical implementation,” said Dr. Antun Domic, chief technology officer at Synopsys. “IBM’s extensive process development and design know-how makes them an ideal partner for extending our DTCO solution to 3 nanometers and beyond.”

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Automotive semiconductors to reach $73B by 2023, says Semico Research

Automotive electronics are a bright light for the semiconductor industry, as smartphone growth slows, and personal computing growth continues to decline. The expectation is that automotive electronics will become the next big technology market driver. The automotive semiconductor market will exceed the overall industry growth as semiconductor content expands with added features and functionality. The desire to put self-driving vehicles on the road is creating increased interest in innovative automotive solutions as well as increased semiconductor demand. A new research report from Semico Research, Automotive Semiconductors: Accelerating in the Fast Lane, states that the automotive segment of the semiconductor industry will grow to $73 billion by 2023.

“There are a number of challenges in the automotive industry that are unique for the system developers to navigate. Autonomous driving is a critical one,” says Jim Feldhan, President of Semico Research. “Many people feel AI is the key to the success of autonomous driving. Autonomous driving includes the ability to have optical character recognition, i.e. reading signs, distinguishing a sign from a person, and determining if the brakes should be turned on. Security surveillance, computer vision, virtual reality and image processing, real-time diagnosis and corrective solutions and strategic map planning are critical to autonomous driving. Increasing levels of processing are required as these systems become more sophisticated.”

Key findings in the report include:

The TAM market for automotive IP processor royalties will grow to $2.34 billion by 2023.
A fully autonomous vehicle (L5) is expected to require 74GB DRAM and 1TB NAND memory.
Powertrain requires the highest compute function and carries the highest ASP.

Revenue generated from processors in Autonomous Driving Systems will reach $422 million in 2018.
In its recent report, Automotive Semiconductors: Accelerating in the Fast Lane (MP118-18), Semico Research provides a comprehensive review of the current market and future opportunities for the semiconductor industry in the automotive segment. Topics covered in the report include Automotive Trends, Opportunities and Challenges, Manufacturing Technology for Auto ICs, Automotive Forecast, and Semiconductor IP in Automotive. The report is 56 pages long and includes 28 tables and 34 figures.

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Cabot Microelectronics to acquire KMG Chemicals

Cabot Microelectronics Corporation (Nasdaq: CCMP), a supplier of chemical mechanical planarization (CMP) polishing slurries and second largest CMP pads supplier to the semiconductor industry, and KMG Chemicals, Inc. (NYSE: KMG), a global provider of specialty chemicals and performance materials, have entered into a definitive agreement under which Cabot Microelectronics will acquire KMG in a cash and stock transaction with a total enterprise value of approximately $1.6 billion. Under the terms of the agreement, KMG shareholders will be entitled to receive, per KMG share, $55.65 in cash and 0.2000 of a share of Cabot Microelectronics common stock, which represents an implied per share value of $79.50 based on the volume weighted average closing price of Cabot Microelectronics common stock over the 20-day trading period ended on August 13, 2018.  The transaction has been unanimously approved by the Boards of Directors of both companies and is expected to close near the end of calendar year 2018.

The combined company is expected to have annual revenues of approximately $1 billion and approximately $320 million in EBITDA, including synergies, extending and strengthening Cabot Microelectronics’ position as one of the leading suppliers of consumable materials to the semiconductor industry.  Additionally, the combined company will be a leading global provider of performance products and services for improving pipeline operations and optimizing throughput.

“We are excited about the combination of two world-class organizations with dedicated and talented employees that provide innovative, high quality solutions to solve our customers’ most demanding challenges,” said David Li, President and CEO of Cabot Microelectronics. “KMG’s industry-leading electronic materials business is highly complementary to our CMP product portfolio, while its performance materials business broadens our product offerings into the fast-growing industry for pipeline performance products and services.  We welcome KMG’s employees to our team and look forward to our future together as one company.”

Chris Fraser, KMG Chairman and CEO, said, “This is an outstanding combination, bringing together two leading companies that will benefit from increased size, scale and geographic reach. For KMG shareholders, this transaction creates significant and immediate value while also providing participation in the future growth of the combined company.  Thanks to the dedication and hard work of KMG employees around the world, KMG has achieved significant progress over the past several years, and I am confident that Cabot Microelectronics will continue to build on this success to further enhance value for our shareholders.”

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pSemi announces world’s first monolithic, SOI Wi-Fi front-end module

pSemi Corporation (formerly Peregrine Semiconductor), a Murata company focused on semiconductor integration, introduces the world’s first monolithic, silicon-on-insulator (SOI) Wi-Fi front-end module (FEM)—the PE561221. Ideal for Wi-Fi home gateways, routers and set-top boxes, this high-performance module uses a smart bias circuit to deliver a high linearity signal and excellent long-packet error vector magnitude (EVM) performance. The PE561221 combines the intelligent integration capabilities of pSemi’s SOI technology and Murata’s expertise in Wi-Fi connectivity solutions and advanced packaging. This 2.4 GHz Wi-Fi FEM integrates a low-noise amplifier (LNA), a power amplifier (PA) and two RF switches (SP4T, SP3T). The monolithic die uses a compact 16-pin, 2 x 2 mm LGA package ideal for either stand-alone use or in 4 x 4 MIMO and 8 x 8 MIMO modules.

“The new IEEE 802.11ax standard is utilizing high-order modulation schemes (1024 QAM) with demanding EVM requirements,” says Colin Hunt, vice president of worldwide sales at pSemi. “Traditional process technologies struggle to keep up with both performance and integration requirements, and only SOI can offer the ideal combination of integration and high performance. This new monolithic Wi-Fi module is a great example of the types of technology and product advancements pSemi and Murata can accomplish together.”

The 2.4 GHz Wi-Fi FEM is based on pSemi’s UltraCMOS® technology platform—a patented, advanced form of SOI. With its outstanding RF and microwave properties, SOI is an ideal substrate for integration. When paired with high-volume CMOS manufacturing—the most widely used semiconductor technology—the result is a reliable, repeatable technology platform that offers superior performance compared to other mixed-signal processes. UltraCMOS technology also enables intelligent integration—the unique design ability to integrate RF, digital and analog components on a single die.

Features, Packaging and Availability 

The PE561221 leverages the intelligent integration capabilities of UltraCMOS technology to deliver exceptional performance, low power consumption and high reliability with 2 kV HBM ESD rating. Through advanced analog and digital design techniques, the Wi-Fi FEM delivers excellent long-packet EVM performance with less than 0.1 dB of gain droop while operating across the entire -40°C to 85°C temperature range. At -40 dB EVM (MCS9), the output power is +19 dBm with less than 0.05 dBm droop in power output after a 4 milliseconds packet. The IC delivers best-in-class dynamic error vector magnitude (DEVM) and current consumption without requiring digital pre-distortion (DPD), and it has excellent MCS11 performance for 802.11ax applications.

Volume-production parts and samples of the PE561221 are available from pSemi. For sales information, please contact sales@psemi.com.

The PE561221 is the first product in the pSemi Wi-Fi FEM portfolio; the product roadmap includes 5 GHz Wi-Fi FEM solutions.

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NSF awards $1.2M to Rochester Institute of Technology, University of California-San Diego, University of Delaware

The American Institute for Manufacturing Integrated Photonics (AIM Photonics), a public-private partnership headquartered in New York State to advance the nation’s photonics manufacturing capabilities, today announced that three National Science Foundation (NSF) funded grants totaling $1.2 million will enable collaborative photonics-centered R&D with the Rochester Institute of Technology (RIT), University of California-San Diego (UCSD), and University of Delaware (UD), respectively.

“AIM Photonics is thrilled to work with leading academic institutions including RIT, UCSD, and UD on these three separate, NSF-funded projects to collaboratively enable photonics-focused devices and capabilities that can allow for the more efficient identification of materials, as well as enhanced processes for manufacturing complex photonic devices and next-generation computing capabilities. We are proud to be the central driver of photonics-based advances that can significantly improve the technologies our society depends on,” said Dr. Michael Liehr, CEO of AIM Photonics.

“Partnering with AIM Photonics provides NSF-funded researchers unique access to world-class manufacturing facilities, stimulating innovation and enabling faculty to span the spectrum from fundamental research breakthroughs to translational advances in integrated photonics devices and circuits that directly impact society,” said Dr. Filbert Bartoli, Director of the Division of Electrical, Communications and Cyber Systems in NSF’s Directorate for Engineering.

Rochester Institute of Technology – AIM Photonics Project

The NSF awarded RIT $423,000 as part of the research project, “PIC: Hybrid Silicon Electronic-Photonic Integrated Neuromorphic Networks,” which will focus on realizing high-performance neural networks that will be integrated onto photonic chips for scalable and efficient architectures that, in tandem with integrated electronics, overcome challenges related to photonic memory and amplification—offering a hybrid, high-bandwidth computing approach for applications to autonomous systems, information networks, cybersecurity, and robotics. To develop these architectures, RIT will work with AIM Photonics to use its leading-edge PIC toolset, located at SUNY Polytechnic Institute in Albany, NY, and the AIM Photonics TAP facility in Rochester, NY—the world’s first 300mm open access PIC Test, Assembly, and Packaging (TAP) facility. The project will take place within RIT’s Future Photon Initiative (FPI) and Center for Human-Aware AI (CHAI).

This research effort will also provide educational opportunities for elementary through high school, undergraduate, and graduate students, and the AIM Photonics Academy will be able to disseminate the project’s findings to further increase understanding of this fast-growing area of research.

“We are excited to partner with AIM Photonics on this research project. The hybrid electronic-photonic neuromorphic chips my Co-PI (Professor Dhireesha Kudithipudi) and I are developing are directly enabled by the state-of-the-art PIC and TAP capabilities of AIM Photonics,” said Project Principal Investigator, Professor Stefan Preble at Rochester Institute of Technology’s Kate Gleason College of Engineering.

University of California-San Diego – AIM Photonics Project 

The NSF awarded UCSD $405,000 for research entitled, “PIC: Mobile in Situ Fourier Transform Spectrometer on a Chip,” which will enable UCSD to rapidly prototype and test miniaturized and mobile platform-embedded optical spectrometers that will excel at chemical identification. The initial design, fabrication, and validation of such a spectrometer on a Si chip have been recently reported in Nature Communications 9:665 (2018). This effort will continue and culminate with full-scale manufacturing runs at AIM Photonics’ foundry at the Albany Nanotech Complex. The integrated chip-scale Fourier transform spectrometer is to be fully CMOS compatible for use in mobile phones and other mobile platforms with potential impacts in areas ranging from environmental management, medicine, and security.

Undergraduate and graduate students at the institution will also be able to gain hands-on training as the research project simultaneously serves as a community outreach tool to inspire students attending middle and high schools.

Moreover, we are also developing an educational silicon photonics kit through the NSF’s ERC-CIAN (Engineering Research Center for Integrated Access Networks) and in collaboration with Tyndall National Institute at University College Cork (Ireland). The kit will initially be implemented in an undergraduate lab curriculum with the goal to prepare the future task force through hands-on experience in this evolving field,” said Project Principal Investigator, Professor Yeshaiahu Fainman, Cymer Chair in Advanced Optical Technologies and Distinguished Professor at the University of California-San Diego.

University of Delaware – AIM Photonics Project

The NSF awarded UD $360,000 as part of the research project, “PIC: Hybrid Integration of Electro-Optic and Semiconductor Photonic Devices and Circuits with the AIM Photonics Institute.” This effort will allow UD to work with AIM Photonics to leverage the initiative’s expertise and state-of-the-art foundry for the development of new heterogeneous manufacturing processes for photonic devices, using new materials such as Lithium Niobate (LiNbO3), which can then be directly integrated with silicon CMOS systems for photonic devices and chip scale systems.

More specifically, the effort aims to realize high performance RF-photonic devices such as ultra-high frequency modulators (> 100 GHz) that are used in data networks; high-efficiency chip-scale routers for advanced data centers; and high-power phased array antenna photonic feed networks that are compatible with older and next-generation wireless communications; in addition to enabling a number of other wide-ranging commercial applications.

“The heterogeneous integration of LiNbO3 with Silicon Photonics allows for the use of the best properties of both material systems, thereby enabling truly innovative systems for countless emerging applications,” said Project Principal Investigator, Dr. Dennis Prather, Engineering Alumni Professor at the University of Delaware.

AIM Photonics features research, development, and commercialization nodes in Albany, NY, at SUNY Polytechnic Institute, as well as in Rochester, NY, where state-of-the-art equipment and tools are being installed at AIM Photonics’ TAP facility. The initiative also includes an outreach and referral network with the University of Rochester, Rochester Institute for Technology, Columbia University, Massachusetts Institute of Technology, University of California – Santa Barbara, University of Arizona, as well as New York State community colleges. In total AIM Photonics includes more than 100 signed members, partners, and additional interested collaborators.

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SEMI integration of ESD Alliance underway

SEMI today announced that all legal requirements have been met for the ESD (Electronic Systems Design) Alliance to become a SEMI Strategic Association Partner.

Full integration of the Redwood City, California-based association representing the semiconductor design ecosystem is expected to be complete by the end of 2018. The integration will extend ESD Alliance’s global reach in the electronics manufacturing supply chain and strengthen engagement and collaboration between the semiconductor design and manufacturing communities worldwide.

As a SEMI Strategic Association Partner, the ESD Alliance will retain its own governance and continue its mission to represent and support companies in the semiconductor design ecosystem.

The ESD Alliance will lead its strategic goals and objectives as part of SEMI, leveraging SEMI’s robust global resources including seven regional offices, expositions and conferences, technology communities and activities in areas such as advocacy, international standards, environment, health and safety (EH&S) and market statistics.

With the integration, SEMI adds the design segment to its electronics manufacturing supply chain scope, connecting the full ecosystem. The integration is a key step in streamlining SEMI members’ collaboration and connection with the electronic system design, IP and fabless communities. The Strategic Association Partnership will also enhance collaboration and innovation across the collective SEMI membership as ESD Alliance members bring key capabilities to SEMI’s vertical application platforms such as Smart Transportation, Smart Manufacturing and Smart Data as well as applications including AI and Machine Learning.

“The addition of ESD Alliance as a SEMI Strategic Association Partner is a milestone in our mission to drive new efficiencies across the full global electronics design and manufacturing supply chain for greater collaboration and innovation,” said Ajit Manocha, president and CEO of SEMI. “This partnership provides opportunities for all SEMI members for accelerated growth and new business opportunities in end-market applications. We welcome ESD Alliance members to the SEMI family.”

“Our members are excited about becoming part of SEMI’s broad community that spans the electronics manufacturing supply chain,” said Bob Smith, executive director of the ESD Alliance. “Global collaboration between design and manufacturing is a requirement for success with today’s complex electronic products. Our new role at SEMI will help develop and strengthen the connections between the design and manufacturing communities.”

All ESD Alliance member companies, including global leaders ARM, Cadence, Mentor, a Siemens business, and Synopsys, will join SEMI’s global membership of more than 2,000 companies while retaining ESD Alliance’s distinct self-governed community within SEMI.

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TowerJazz to hold Technical Global Symposium (TGS) in China

TowerJazz, the global specialty foundry, announced details of its China Technical Global Symposium (TGS) event in Shanghai on August 22, 2018, focusing on the company’s analog technology offerings, advanced manufacturing solutions and commitment to customer partnerships.

In addition, TowerJazz has launched its official “WeChat” account, the most popular communication app in China, enabling the Company to support the growing activities in China while increasing interaction with Chinese users and sharing the latest TowerJazz technology information, news and events.

“China is a strong region for TowerJazz with on-going increased activities and we are answering the growing demand of Chinese players with our various advanced analog platforms, including Radio Frequency (RF) & High Performance Analog (HPA), power management, and CMOS image sensors (CIS), targeting fast growing markets such as automotive, sensors, the IoT, and 5G, among others,” said Qin Lei, TowerJazz China Country Manager. “In addition, we are pleased to launch our “WeChat” account to better reach and network with our existing and potential Chinese customers.”

Company executives and experts will provide technical sessions on TowerJazz’s leading specialty process technologies such as: RF SOI and SiGe for wireless handsets and the IoT, high performance SiGe for optical networking, 5G, mmWave and automotive applications, silicon photonics (SiPho) technology for optical networks, 65nm CMOS technology with embedded NVM solutions, 0.18um and 65nm BCD focusing on low voltage power products, and CMOS image sensors for face recognition and automotive.

TowerJazz will also present the latest design enablement tools and solutions jointly developed with its EDA partners, and its sponsors Mentor, Empyrean, Silvaco and Xpeedic Technology will share the latest design capabilities offered in collaboration with TowerJazz.

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Size of semiconductor acquisitions may have hit limit

The demise of Qualcomm’s pending $44 billion purchase of NXP Semiconductors in late July along with growing regulatory reviews of chip merger agreements, efforts by countries to protect domestic technology, and the escalation of global trade friction all suggest semiconductor acquisitions are hitting a ceiling in the size of doable deals.  It is becoming less likely that semiconductor acquisitions over $40 billion can be completed or even attempted in the current geopolitical environment and brewing battles over global trade.

IC Insights believes a combination of factors—including the growing high dollar value of major chip merger agreements, complexities in combining large businesses together, and greater scrutiny of governments protecting their domestic base of suppliers—will stifle ever-larger mega-transactions in the semiconductor industry in the foreseeable future.  Figure 1 ranks the 10 largest semiconductor merger and acquisition announcements and underscores the growth in size of these M&A transactions.  Eight of the 10 largest announcements occurred in the last three years with only the biggest deal (Qualcomm buying NXP) failing to be completed.

Figure 1

It is important to note that IC Insights’ M&A list only covers semiconductor suppliers, chipmakers, and providers of integrated circuit intellectual property (IP) and excludes acquisitions of software and system-level businesses by IC companies  (such as Intel’s $15.3 billion purchase of Mobileye, an Israeli-based developer of digital imaging technology for autonomous vehicles, in August 2017).  This M&A list also excludes transactions involving semiconductor capital equipment suppliers, material producers, chip packaging and testing companies, and design automation software firms.

Qualcomm’s $44 billion cash purchase of NXP would have been the largest semiconductor acquisition ever if it was completed, but the deal—originally announced in October 2016 at nearly $39 billion and raised to $44 billion in February 2018—was canceled in the last week of July because China had not cleared the transaction.  China was the last country needed for an approval of the merger, and it was believed to be close to clearing the purchase in 2Q18, but growing threats of tariffs in a brewing trade war with the U.S. and moves to block Chinese acquisitions of American IC companies caused China to taken no action on the $44 billion acquisition in time for a deadline set by Qualcomm and NXP.  U.S.-based Qualcomm canceled the acquisition on July 26 and quickly paid NXP in the Netherlands a $2 billion breakup fee so the two companies could move on separately.

Prior to Qualcomm’s failed $44 billion offer for NXP, the largest semiconductor acquisition was Avago Technologies’ $37 billion cash and stock purchase of Broadcom in early 2016.  Avago renamed itself Broadcom Limited after the purchase and launched a failed $121 billion hostile takeover bid for Qualcomm at the end of 2017.  It lowered the unsolicited bid to $117 billion in February 2018 after Qualcomm raised its offer for NXP to $44 billion.  In March 2018, U.S. President Donald Trump blocked Broadcom’s $117 billion takeover bid for Qualcomm after concerns were raised in the U.S. government about the potential loss of cellular technology leadership to Chinese companies, if the hostile acquisition was completed. After the presidential order, Broadcom executives said the company was considering other acquisition targets, with cash, that would be smaller and more focused.

The global semiconductor industry has been reshaped by a historic wave of mergers and acquisitions during the past three years, with about 100 M&A agreements being reached between 2015 and the middle of 2018 with the combined value of these transactions being more than $245 billion, based on data collected by IC Insights and contained within its Strategic Reviews database subscription service and in The 2018 McClean Report on the IC Industry.  A record-high $107.3 billion in semiconductor acquisition agreements were announced in 2015.  The second highest total for semiconductor M&A agreements was then reached in 2016 at $99.8 billion.   Semiconductor acquisition announcements reached a total value of $28.3 billion in 2017, which was twice the industry’s annual average of about $12.6 billion in the first half of this decade but significantly less than 2015 and 2016, when M&A was sweeping through the chip industry at historic levels.  In the first six months of 2018, semiconductor acquisition announcements had a total value of about $9.6 billion, based on IC Insights’ running tally of announced M&A deals.

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Strong 2Q’18 global supply chain growth but second half slowing

By Walt Custer

2Q’18 Electronic Supply Chain Growth Update

  • Chart 1 is a preliminary estimate of global growth of the electronic supply chain by sector for 2Q’18 vs 2Q’17. Note the strong performance of semiconductors, SEMI capital equipment and passive components.
  • Chart 2 gives preliminary 2Q’18 world electronic equipment growth by type. Global electronic equipment sales rose an estimated 9%+ when consolidated into US dollars in the second quarter of this year compared to the same quarter in 2017.
  • Based on this, data global electronic equipment sales growth appears to have now peaked on a 3/12 growth basis for this present business cycle (Chart 3).

As a caution these charts are based on a combination of actual company financial reports and estimates for companies that have not yet reported their calendar second quarter financial results. A number of large companies have yet to report but these early estimates have historically been close to final growth values.  We will update Chart 1 next month.

Semiconductor Capital Equipment Business Cycle

  • Semiconductor capital equipment sales are historically very volatile, with their growth fluctuating MUCH MORE than electronic equipment (Chart 4). However, both series appear to have peaked on a 3/12 basis for this current cycle.

  • Semiconductors, SEMI capital equipment and Taiwan chip foundry sales all are seeing slower growth. 3/12 values >1 still indicate an expansion but slower growth is indicated.

Supply chain performance in the second half of this year bears careful watching!

Walt Custer of Custer Consulting Group is an analyst focused on the global electronics industry.

Originally published on the SEMI blog.

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Keysight Technologies acquires Thales Calibration Services

Keysight Technologies, Inc. (NYSE: KEYS), a technology company that helps enterprises, service providers, and governments accelerate innovation to connect and secure the world, has acquired Thales Calibration Services in Melbourne, Australia, a subsidiary of Thales Group, effective July 2, 2018. This acquisition establishes Keysight as the largest calibration and support services organization in Australia.

Thales Calibration Services is a world-class commercial calibration facility specializing in dimensional, pressure, mass, and temperature metrology. Located in Melbourne, Thales Calibration was originally established to provide dimensional support, but expanded its capabilities and accreditation over the past several decades. It is now the largest commercial non-electronic metrology lab in Australia servicing the defense, commercial, medical, petro-chemical, and pharmaceutical industries.

“This acquisition complements our existing electrical portfolio, creating new opportunities for Keysight to support the defense sector in Australia,” said Bor-Chun Gooi, general manager for Keysight’s Managed Services Division East. “Now, Keysight is the largest calibration provider in Australia, offering customers a one stop services solution provider.”

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Terahertz technology creates new insight into how semiconductor lasers work

Pioneering engineers working with terahertz frequency technology have been researching how individual frequencies are selected when a laser is turned on, and how quickly the selection is made.

The development of specific terahertz equipment has allowed them to investigate this process for the first time. Their results, published in Nature Communications, will underpin the future development of semiconductor lasers, including those used in public and private sector-owned telecommunications systems.

For many years, it has been predicted that operating frequencies within semiconductor lasers stabilise on a timescale of a few nanoseconds (ie a few billionths of a second) and can be changed within a few hundreds of picoseconds (ie thousandths of a nanosecond).

Until now, though, no detector has been capable of measuring and proving this precisely, and the best results have only been achieved on nanosecond timescales, which are too slow to allow really efficient analysis or to be used to develop the most effective new systems.

The University of Leeds researchers, working with international colleagues at École Normal Supérieure in Paris, France and the University of Queensland in Brisbane, Australia have now used terahertz frequency quantum cascade lasers and a technique called terahertz time-domain spectroscopy to understand this laser stabilisation process.

The terahertz-powered technology can measure the wavelength of light in periods of femtoseconds (ie millionths of a nanosecond) giving unprecedented levels of detail. By knowing the speed at which wavelengths change within lasers, and what happens during that process within miniscule time frames, more efficient devices and systems can be built.

The Leeds elements of the study were carried out in the University’s Terahertz Photonics Laboratory, part of the University’s Bragg Centre for Materials Research.

Dr Iman Kundu, principal author of the research paper explaining the group’s findings, said: “We’ve exploited the ultrafast detection capabilities of terahertz technology to watch laser emissions evolve from multiple colours to a single wavelength over less than a billionth of a second.

“Now that we can see the detailed emission of the lasers over such incredibly small time frames, we can see how the wavelength of light changes as one moves from one steady state to a new steady state.

“The benefits for commercial systems designers are potentially significant. Terahertz technology isn’t available to many sectors, but we believe its value lies in being able to highlight trends and explain the detailed operation of integrated photonic devices, which are used in complex imaging systems which might be found in the pharmaceutical or electronics sectors.

“Designers can then apply these findings to lasers operating at different parts of the electromagnetic spectrum, as the underlying physics will be very similar.”

Professor Edmund Linfield, Chair of Terahertz Electronics at the University of Leeds, who was also involved in the study said: “We’re using the highly advanced capabilities of terahertz technology to shine a light on the operation of lasers.

“Our research is aimed at showing engineers and developers where to look to drive increased performance in their own systems. By doing this, we will increase the global competitiveness of the UK’s science and engineering base.”

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CyberOptics demonstrates Airborne Particle and Ultra High-Resolution MRS sensors at SEMICON Taiwan

CyberOptics® Corporation (NASDAQ: CYBE), a global developer and manufacturer of high precision 3D sensing technology solutions, announces it will demonstrate its next generation Airborne Particle Sensor™ technology (APS3) 300mm with new ParticleSpectrum™ software at SEMICON Taiwan, September 5-7 at the Nangang Exhibition Center in Taipei in booth #L312.

CyberOptics’ WaferSense® APS3 speeds equipment set-up and long-term yields in semiconductor fabs by wirelessly detecting, identifying and monitoring airborne particles. Now in a thinner and lighter form factor to travel through semiconductor tools with ease, the APS3 offers leading accuracy and sensitivity valued by equipment and process engineers.

“Semiconductor fabs worldwide have adopted our Airborne Particle Sensors,” said Dr. Subodh Kulkarni, President and CEO, CyberOptics. “We have further advanced the technology that they rely on to significantly improve their yields and tool uptime.”

The APS3 solution incorporates ParticleSpectrum software – a completely new, touch-enabled interface with user-friendly functionality, making it simple to read, record and review small to large airborne particle data and see the effects of cleanings, adjustments and repairs in real-time.

At SEMICON Taiwan, CyberOptics will also demonstrate the proprietary 3D Ultra High-Resolution Multi-Reflection Suppression (MRS) Sensor technology that meticulously identifies and rejects reflections caused by shiny components and surfaces. Effective suppression of multiple reflections is critical for highly accurate measurements. Offering an unmatched combination of accuracy and speed, MRS sensors are widely used for inspection and measurement in the SMT, metrology and in semiconductor markets. This best in class, ultra high-resolution technology used in back-end inspection applications, is ideally suited for IC package, wafer bump inspection and mid-end semiconductor applications where the highest degree of precision is required.

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Rudolph Technologies appoints David B. Miller as Chairman of the Board

Rudolph Technologies, Inc. announces the appointment of David B. Miller to the role of Chairman of the Board of Directors with an effective date of August 5, 2018. Mr. Miller’s appointment is subsequent to the Company’s receipt of Thomas G. Greig’s resignation from the position.

“I am grateful for and enjoyed the opportunity to have served as Lead Director and Chairman of the Rudolph Board of Directors,” said Tom Greig. “Dave Miller brings the right skills and industry background to the chairmanship role in order to continue to drive Rudolph’s success. I look forward to supporting him as I continue to serve on our Board of Directors.”

“We greatly appreciate Tom Greig’s leadership over the past six years and his ongoing service,” commented Michael Plisinski, chief executive officer, Rudolph Technologies. “We are pleased to have Dave Miller’s leadership as Chairman while the company continues to focus on the strategy to build a well-balanced and sustainable growth company.”

Mr. Miller, who has been an independent member of Rudolph’s Board for three years, brings significant leadership and practical experience to the chairmanship role. This experience includes over 40 years within the electronics industry, including six years as president of DuPont Electronics & Communications, as well as prior service on the board of SEMI International. He brings to the role a broad international perspective and understanding of global semiconductor and display markets which have been cultivated not only from his global work experience but also as a result of residing in Asia for three years. Mr. Miller’s experience and leadership will further the market growth of Rudolph as it continues to drive its position as a vital supplier within the semiconductor value chain.

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ClassOne places Solstice CopperMax electroplating tool with defense industry supplier i3 Microsystems

ClassOne, a supplier of new electroplating and wet process tools to the 200mm and smaller semiconductor manufacturing industry, today announced the sale its flagship Solstice® S8 CopperMax™ electroplating tool to i3 of Binghamton, NY.  i3 is rapidly expanding its St. Petersburg, FL facility to accommodate volume production work, and they need an automated plating tool with the ability to grow in tandem. CopperMax™ has been chosen to cost-effectively automate the facility’s wet-bench electroplating processes, with flexibility to easily add related downstream processes.

“i3 has selected CopperMax™ for several excellent reasons,” said ClassOne CEO Byron Exarcos. “Our proprietary CopperMax™ cation exchange membrane technology is simply unrivaled in this market. The plating chamber has been designed to dramatically reduce consumables cost while maintaining extremely high levels of feature quality—even for challenging deposition processes such as TSV. CopperMax customers routinely see reductions in additive consumables cost approaching 95%. What’s more, our Solstice platform is engineered for easy expansion, and is designed to support multiple independent processes simultaneously. It’s a perfect fit for facilities that want to grow beyond wet bench work.”

The Solstice S8 CopperMax platform can be configured with from 2 to 8 entirely independent, field-retrofittable process chambers. CopperMax™ also supports multiple wafer sizes simultaneously, allowing i3 to easily migrate from 4- to 6-inch wafers as their production requirements change. i3 will be working with ClassOne to add Solvent and UBM processing chambers to the same CopperMax™ tool in the coming months.

“CopperMax is a perfect fit for our needs,” said Neal Driver, VP-General Manager of i3 Microsystems. “The tool is incredibly flexible and will grow with us as we expand our production environment. We have also been impressed by ClassOne’s outstanding commitment to helping us develop and perfect our deposition processes. They’ve made a serious corporate commitment to customer service, and it shows.”

i3 is a highly-secure, vertically-integrated semiconductor supplier to the defense and aerospace industries. With Solstice® platforms now in production at several of the world’s foremost defense contractors, ClassOne has emerged as the supplier of choice for the exacting requirements of the defense and aerospace industries.

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DRAM sales forecast to top $100B this year with 39% market growth

IC Insights recently released its Mid-Year Update to The McClean Report 2018.  The update includes a revised forecast of the largest and fastest-growing IC product categories this year.  Sales and unit growth rates are shown for each of the 33 IC product categories defined by the World Semiconductor Trade Statistics (WSTS) organization in the Mid-Year Update.

The five largest IC product categories in terms of sales revenue and unit shipments are shown in Figure 1.  With forecast sales of $101.6 billion, (39% growth) the DRAM market is expected to be the largest of all IC product categories in 2018, repeating the ranking it held last year.  If the sales level is achieved, it would mark the first time an individual IC product category has surpassed $100.0 billion in annual sales. The DRAM market is forecast to account for 24% of IC sales in 2018.  The NAND flash market is expected to achieve the second-largest revenue level with total sales of $62.6 billion this year. Taken together, the two memory categories are forecast to account for 38% of the total $428.0 billion IC market in 2018.

Figure 1

For many years, the standard PC/server MPU category topped the list of largest IC product segments, but with ongoing increases in memory average selling prices, the MPU category is expected to slip to the third position in 2018.  In the Mid-Year Update, IC Insights slightly raises its forecast for 2018 sales in the MPU category to show revenues increasing 5% to an all-time high of $50.8 billion, after a 6% increase in 2017 to the current record high of $48.5 billion.  Helping drive sales this year are AI-controlled systems and data-sharing applications over the Internet of Things.  Cloud computing, machine learning, and the expected tidal wave of data traffic coming from connected systems and sensors is also fueling MPU sales growth this year.

Two special purpose logic categories—computer and peripherals, and wireless communications—are forecast to round out the top five largest product categories for 2018.

Four of the five largest categories in terms of unit shipments are forecast to be some type of analog device.  Total analog units are expected to account for 54% of the total 318.1 billion IC shipments forecast to ship this year.  Power management analog devices are projected to account for 22% of total IC units and are forecast to exceed the combined unit shipment total of the next three categories on the list.  As the name implies, power management analog ICs help regulate power usage and to keep ICs and systems running cooler, to manage power usage, and ultimately to help extend battery life—essential qualities for an increasingly mobile and battery-powered world of devices.

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European electronics industry CEOs call on European Commission to bolster sector’s competitiveness

By Laith Altimime

In a bid to reinvigorate Europe’s electronics strategy and strengthen the region’s position in key emerging technologies, European electronics industry CEOs in June called on public and private actors to accelerate collaboration at the European Union and national levels. The CEO’s proposed new strategic actions include creating a European Design Alliance to pool the expertise of design houses and forming an electronics education and skills task force consisting of representatives from industry, research, European institutions, member states and SEMI.

The business executive’s calls – embodied in “Boosting Electronics Value Chain in Europe, a report submitted to Mariya Gabriel, Commissioner for Digital Economy and Society, of the European Commission – come as global competition in the electronics industry intensifies. The document highlights Europe’s need to buttress its position in artificial intelligence (AI), autonomous driving and personalized healthcare – applications that rely on new semiconductor architectures, materials, equipment and design methodologies.

The European semiconductor industry plans to pour more than 50 billion EUR into technology development and innovation by 2025, deepening its investments in research, innovation and manufacturing to help drive Europe’s digital transformation.

For its part, SEMI, as the industry association connecting the electronics value chain, is well-positioned to bring together member companies and public actors to address key challenges facing the sector. This year in April, SEMI announced that Electronics System Design Alliance (ESD Alliance) will join SEMI, adding key electronics design companies to SEMI membership and unlocking the full potential of collaboration between electronics design and manufacturing.  With the ESD Alliance, SEMI adds the product design segment to the electronics supply chain, streamlining and connecting the full ecosystem. The integration also promises to support the industry coordination required to develop specialized (AI) chips used in various smart applications.

SEMI Europe is also accelerating its education and workforce development activities. SEMI Europe this year created its Workforce Development Council Europe, chaired by Emir Demircan, SEMI Europe’s senior manager of public policy, based in Brussels. The council is designed to connect electronics industry human resources representatives with members to evolve best practices in hiring that help Europe gain, train and retain world-class talent.

Other SEMI Europe workforce development activities include the following:

  • SEMI member forums across Europe are helping young talent with career opportunities in the semiconductor industry.
  • In November, SEMICON Europa will host a Career Café where STEM students will explore careers in electronics design and manufacturing.
  • With the participation of representatives from the European Commission, SEMI Europe’s Industry Strategy Symposium in April focused on strategies for attracting more skilled workers into electronics design and manufacturing.

Looking ahead, semiconductor sales is forecast to reach USD 1 trillion by 2030. The global semiconductor industry is at the heart a new era of connectivity, developing breakthrough solutions for ascendant data-driven technologies such as AI and Internet of Things (IoT). SEMI Europe’s role in strengthening the region’s position in the global electronics industry to help drive this extraordinary growth is critical. SEMI Europe will continue to foster public-private partnerships to tackle industry challenges that are too big, too risky and too costly for companies and government institutions to address alone.

Contact: Laith Altimime, President, SEMI Europe, laltimime@semi.org ; Emir Demircan, Sr Manager Public Policy, edemircan@semi.org

Originally published on the SEMI blog.

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SEMI China, CASPA promote China-Silicon Valley innovation partnership

By Cherry Sun

Aiming to forge stronger ties between the two technology heavyweights as partners in semiconductor industry innovation, SEMI and CASPA (Chinese American Semiconductor Professional Association) in mid July signed a strategic cooperation agreement to promote industry innovation between Silicon Valley and China. Under the agreement, SEMI and CASPA will work to connect Silicon Valley and China industry resources and encourage greater collaboration.

The agreement, signed at the “SIIP China Innovation and Investment Forum: Innovation at Scale: from IoT, Cloud to AI & ADAS” in Silicon Valley, supports key SEMI principles including free trade, open markets, intellectual property protection, global cooperation and innovation, said SEMI China president Lung Chu.

Brandon Wang, president and chairman of CASPA, and Lung Chu, SEMI China president, sign strategic cooperation agreement.

Speaking at the event attended by more 200 industry executives and visionaries, Chu noted that with 2019 expected to be another record year for fab and equipment investment and the semiconductor on track to reach $500 billion by next year, the time is ripe for greater cooperation between Silicon Valley and China. China and South Korea (Samsung) are driving sharp growth in global semiconductor equipment sales.

The global artificial intelligence (AI) industry is taking shape with companies ranging from startups and multinationals to semiconductor and Internet providers investing in AI research and development as China and the United States make the heaviest AI investments of all regions. A plethora of AI applications enabled by 5G will spur even greater IC demand.

Opening the event, SEMI president and CEO Ajit Manocha noted that technologies such as AI, Internet of Things (IoT) will transform our lives and that semiconductor industry leaders must cultivate a new generation of innovators to ensure continued industry growth.

Mark Ding, CEO of Shanghai Industrial Technology Research Institute (SITRI), said China is well-positioned to help goose semiconductor industry growth with its ample capital, lower capital expenditures and strong local market. He also noted that three keys to innovation are platforms, talent and capital.

Dr. Naveed Shervani, CEO of SiFive, the first fabless semiconductor company to build customized silicon based on the free and open RISC-V instruction set architecture, proposed goals for future semiconductor industry growth including reducing IC and IP costs and cutting design time.

Stuart Ching, VP of KULR Technology, a provider of thermal management technologies, pointed to the importance of lithium batteries. Those with higher energy density and lower cost would promote a range of power applications for mobile electronic equipment and lead to the mass production of solid-state batteries between 2023 and 2025.

Originally published on the SEMI blog.

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Average design cost for basic SoCs across all geometries was $1.7M in 2017, says Semico Research

The semiconductor industry today is faced with several substantial issues-not the least of which are the continuing rise in design costs for complex SoCs, the decrease in the incidence of first-time-right designs and the increase in the design cycle time against shrinking market windows and decreasing product life cycles. An additional factor has now been added to SoC design costs with the emergence of very complicated software applications intended to run on the SoC silicon. The costs of the software effort have outstripped the silicon design costs and have become the major part of the cost of these designs. IP integration is also a growing part of design costs. Semico’s new report SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts addresses these and many other design concerns while reporting that the average design cost for Basic SoCs across all geometries in 2017 was $1.7 million.

“Analysis of design activity for the three types of SoC profiled in this report shows that while design costs at new nodes continue to increase, the average design cost at each node is not increasing as quickly, giving room for designers to still accomplish their silicon solutions at reasonable costs if they are prudent in their design selection,” says Rich Wawrzyniak, Sr. Market Analyst for ASIC & SoC at Semico. “For each of the three types of SoC there is still considerable activity at the older nodes of 90nm, 65nm and 40nm. Costs at these geometries are much less than at 10nm and 7nm so even though these newer designs cost much more, the average for all SoCs has dropped due to the increase in new designs for Basic SoC.”

Key findings of the report include:

  • The average design cost for Value Multicore SoCs across all geometries was $4.8M in 2017.
  • The average design cost for all SoCs across all geometries is forecast to increase to $5.3M by 2023.
  • The number of ‘first-time-right’ designs has dropped at every process geometry since the 180nm node.
  • Silicon design costs at the 7nm node for an Advanced Performance Multicore SoC first-time effort are projected to be 23% higher than at the 10nm node.

In a unique, insightful look at this constantly evolving market, Semico Research’s new report, SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts, examines the primary forces and integration pressures that are driving this market today in 135 pages, with 41 tables and 64 graphs. This study analyzes many important questions facing the semiconductor industry today including:

  • What is the current cost for a Complex System-on-a-Chip (SoC) design, and what will it be in the near future?
  • Is it possible to do SoC designs without maximizing the costs for these designs?
  • What is the incidence of ‘first-time-right’ for these designs today and in the near future?
  • How is the design cycle time for these designs changing?
  • How do complicated software applications impact the design costs?
  • How fast are IP integration costs rising, and how high will they go?
  • What strategies are designers using to cope with rising design costs?
  • What is the average silicon design cost today for each process geometry and SoC type, and how quickly is it rising?
  • What impact will EDA tools that include some artificial intelligence (AI) and machine learning (ML) functionality have on design costs for complex silicon?

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Process Watch: Automotive defect sensitivity requirements

By David W. Price, Douglas G. Sutherland, Jay Rathert, John McCormack and Barry Saville

Author’s Note:The Process Watch series explores key concepts about process control—defect inspection, metrology and data analytics—for the semiconductor industry. This article is the third in a series on process control strategies for automotive semiconductor devices. For this article, we are pleased to include insights from our colleagues at KLA-Tencor, John McCormack and Barry Saville. 

Semiconductors continue to grow in importance in the automotive supply chain, requiring IC manufacturers to adapt their processes to produce chips that meet automotive quality standards. The first article in this seriesfocused on the fact that the same types of IC manufacturing defects that cause yield loss also cause poor chip reliability and can lead to premature failures in the field. To achieve the high reliability required in automotive ICs, additional effort must be taken to ensure that sources of defects are eliminated in the manufacturing process. The second article in this seriesoutlined strategies, such as frequent tool monitoring and a continuous improvement program, that reduce the number of defects added at each step in the IC manufacturing process. This article explores how to drive tool monitoring to a higher level of performance in order to help automotive IC manufacturers achieve chip failure rates below the parts per billion level.

As a reminder, tool monitoring is the established best practice for isolating the source of random defectivity contributed by the fab’s process tools. During tool monitoring, a bare wafer is inspected to establish its baseline defectivity, run through a specific process tool (or chamber), and then inspected again. Any defects that were added to the wafer must have come from that specific process tool. This method can reveal the cleanest “golden” tools in the fab, as well as the “dog” tools that contribute the most defects and require corrective action. With plots of historical defect data from the process tools, goals and milestones for continuous improvement can be implemented.

When semiconductor fabs design their tool monitoring strategy, they must decide on the minimum size of defects that they want to detect and monitor. If historical test results have shown that smaller defects do not impact yield, then fabs will run their inspection tools at a lower sensitivity so that they no longer detect these smaller defects. By doing this, they can focus only on the larger yield-killer defects, avoiding distraction from the smaller “nuisance” defects. This approach works for a consumer fab that is only trying to optimize yield, but what about the automotive fab? Recall that yield and reliability issues are caused by the same defects types – yield and reliability defects differ only in their size and/or where they land on the device pattern.2 Therefore, a tool monitoring strategy that leaves the fab blind to smaller defects may be missing the very defects that will be responsible for future reliability issues.

Moreover, it’s important to understand that defects that seem small and inconsequential at one process layer may have a dramatic impact later in the process flow – their impact can be exacerbated by the subsequent process steps. The two SEM images in figure 1 were taken at exactly the same location on the same wafer, but at different steps of the manufacturing process. The image on the left shows a single, small defect that was found on the wafer after a deposition layer. This defect was previously thought to be a nuisance defect with no negative effect on the die pattern or chip performance. The image on the right shows that same deposition defect after metal 1 pattern formation. The presumed nuisance defect has altered the quality of the metal line printed several process steps later. This chip might pass electrical wafer sort, but this type of metal deformity could easily become a reliability issue in the field when activated by automotive environmental stressors.

Figure 1. The left image shows small particle created at a deposition layer. The right image shows the exact same location on the wafer after the metal 1 pattern formation. The metal line defect was caused by the small particle at the prior deposition layer. This type of deformity in the metal line could easily become a reliability issue in the field.

So how does an automotive IC fab determine the smallest defect size that will pose a reliability risk? To start, it is important to understand the impact of different defect sizes on reliability. Consider, for example, the different magnitudes of a line open defect shown in figure 2. A chip that has a pattern structure with a full line open will likely fail at electrical wafer sort and thus does not pose any reliability risk. A chip with a 50% line open – a line that is pinched or otherwise restricted to ~50% of its cross-sectional area – will likely pass electrical wafer sort but poses a significant reliability risk in the field. If this chip is used in a car, environmental conditions such as heat, humidity and vibrations, can cause degradation of this defect to a full line open, resulting in chip failure.

Figure 2. The image on the left shows a full line open, while the right image shows a ~50% line open. The chip on the left will fail at sort (assuming there is no redundancy). The chip on the right may pass electrical wafer sort but is a reliability risk in the field.

As a next step, it is important to understand how different size defects affect a chip’s pattern integrity. More specifically, what is the smallest defect that will result in a line open? What is the smallest defect that will result in a 50% line open?

Figure 3 shows the results of a Monte Carlo simulation that models the impact of different size defects introduced at a BEOL film deposition step. Minimum defect size is plotted on the vertical axis against varying metal layer pitch dimensions. This data corresponds to the metal 1 spacing for the 7nm, 10nm, 14nm and 28nm design nodes, respectively.

The green data points correspond to the smallest defects that will cause a full line open and the orange data points correspond to the smallest defects that will produce a 50% line open (i.e., a potential reliability failure). In each case the smallest defect that will cause a potential reliability failure is 50-75% of the smallest defect that will cause a full line open.

Figure 3. The green data points show the minimum defect size required to cause a full line open at the minimum metal pitch. The orange data points show the minimum defect size needed to cause a 50% line open. The x-axis is the metal 1 spacing for the 7nm (far left data point), 10nm, 14nm and 28nm (far right data point) design nodes.

These modeling results imply that to control for, and reduce, the number of reliability defects present in the process, fabs need to capture smaller defects. Therefore, they require higher sensitivity inspections than what is required for yield optimization. In general, detection of reliability defects requires an inspection sensitivity that is one node ahead of the current design node plan for yield alone. Simply put, a fab’s previous standards for reducing defectivity to optimize yield will not be sufficient to optimize reliability.

Increasing the sensitivities of the tool monitoring inspection recipes, or in some cases, using a more capable inspection system, will find smaller defects and possibly reveal previously hidden signatures of defectivity, as in Figure 4 below. While these signatures may have had a tolerable impact on yield in a consumer fab, they represent an unacceptable risk to reliability for automotive fabs pursuing continuous improvement and Zero Defect standards.

Figure 4: Hidden defect signatures that may impact reliability are often revealed with appropriate tool monitoring sensitivity. Zero Defect standards require corrective action on the process tool contributing these defects.

There are several important unpatterned wafer defect inspection factors for a fab to consider when creating a strategy to improve tool monitoring inspection sensitivity to find the small, reliability-related defects contributed by process tools. First, it is important to recognize that in a mature fab where yields are already high, there is rarely a single process layer or module that will be the “silver bullet” to reducing defectivity adequately to meet reliability improvement goals. Rather, it is sum of small gains across many layers that produce the desired gains in reliability. Because yield and the associated reliability improvements are cumulative across layers, reliability gains achieved through process tool monitoring using unpatterned wafer inspection are best demonstrated using a multi-layer regression model:

Yield = f(Ys)+f(SFS1)+f(SFS2)+ f(SFS3)+ ….. f(SFSN) + error

  • Ys = systematic yield loss (not particles related)
  • SFSx = cumulative Sursfcan unpatterned wafer inspection detected particles for many layers
  • Error = Yield loss mechanisms not detected by Surfscan

This implies that reliability improvements require a fab’s commitment to continuous improvement in defectivity levels across all processes and process modules.

Second, the fab should consider the quality of the bare wafer used for process tool monitoring. Recycling bare wafers increases the surface roughness with each cycle, an attribute known as haze. This haze level is fundamentally noise that affects the inspection system’s ability to differentiate the signal of smaller defects. Variability in haze across the population of test wafers acts as a limit to overall inspection recipe capability, requiring normalization, calibration and haze limits to reduce the impact of this noise source on defect sensitivity.

Next, the fab should ensure that the monitor step closely mimics the process that a production, patterned wafer follows. Small time-saving deviations in the monitor wafer flow to short cut the process may inadvertently skip the causal mechanism of defectivity. Furthermore, an over-reliance on mechanical handling checks alone bypasses the process completely and misses the critical contribution the process plays in particle generation.

When increasing the inspection recipe sensitivity, the fab must co-optimize both the “pre” and “post” inspection together. Often cycling the bare wafer through a process step can “decorate” small pre-existing defects on the wafer that were initially below the detection threshold. Once decorated, the defects now appear bigger and are more easily detected. In an unoptimized “post” inspection, these decorated defects can look like “adders,” leading to a false alarm and inadvertent process tool down time. Optimizing the inspections together maximizes the sensitivity and increases the confidence in the excursion alarms while avoiding time-consuming false alarms.

Lastly, it is important to review and classify the defects found during unpatterned inspection to correlate their relevance to the defects found at the equivalent patterned wafer process step. Only then can the fab be confident that the source of the defects has been isolated and appropriate corrective action has been taken.

To meet the high reliability demands of the automotive industry, IC manufacturers will need to go beyond simply monitoring and controlling the number of yield limiting defects on the wafer. They will need to improve the sensitivity of their tool monitoring inspections to one node smaller than what would historically be considered relevant. Only with this extra sensitivity can they detect and eliminate defects that would otherwise escape the fab and cause premature reliability failures. Additionally, when implementing a tool monitoring strategy, fabs need to carefully consider multiple factors, such as monitor wafer recycling, pre and post inspection sensitivity and the importance of a fab-wide continuous improvement program. With so much riding on automotive semiconductor reliability, increased sensitivity to smaller defects is an essential part of an optimal Zero Defect continuous improvement program.

About the Authors:

Dr. David W. Price and Jay Rathert are Senior Directors at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 15 years, they have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall process control strategy for a variety of specific markets, including implementation of strategies for automotive reliability, legacy fab cost and risk optimization, and advanced design rule time-to-market. The Process Watch series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

John McCormack is a Senior Director at KLA-Tencor. Barry Saville is Consulting Engineer at KLA-Tencor. John and Barry both have over 25 years of experience in yield improvement and defectivity reduction, working with many IC manufacturers around the world.

References:

  1. Price, Sutherland and Rathert, “Process Watch: The (Automotive) Problem With Semiconductors,” Solid State Technology, January 2018.
  2. Price, Sutherland and Rathert, “Process Watch: Baseline Yield Predicts Baseline Reliability,” Solid State Technology, March 2018.

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Mid-year global semiconductor sales up 20.4% compared to 2017

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $117.9 billion during the second quarter of 2018, an increase of 6.0 percent over the previous quarter and 20.5 percent more than the second quarter of 2017. Global sales for the month of June 2018 reached $39.3 billion, an uptick of 1.5 percent over last month’s total of $38.7 billion, and a surge of 20.5 percent compared to the June 2017 total of $32.6 billion. Cumulatively, year-to-date sales during the first half of 2018 were 20.4 percent higher than they were at the same point in 2017. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Halfway through 2018, the global semiconductor industry continues to post impressive sales totals, notching its highest-ever quarterly sales in Q2 and record monthly sales in June,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Global sales have increased year-to-year by more than 20 percent for 15 consecutive months, and sales of every major product category increased year-to-year in June. Sales into the Americas market continue to be strong, with year-to-date totals more than 30 percent higher than at the same point last year.”

Regionally, sales increased compared to June 2017 in China (30.7 percent), the Americas (26.7 percent), Europe (15.9 percent), Japan (14.0 percent), and Asia Pacific/All Other (8.6 percent). Sales also were up compared to last month in China (3.2 percent), Japan (1.3 percent), the Americas (1.2 percent), and Asia Pacific/All Other (0.5 percent), but down slightly in Europe (-0.8 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2018 SIA Databook.

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UMC and Avalanche Technology partner for MRAM development and 28nm production

United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) (“UMC”), a global semiconductor foundry, and Avalanche Technology, Inc., the next generation STT-MRAM (Spin Transfer Torque Magnetic RAM) leader, today announced that they have entered a partnership for joint development and production of MRAM to replace embedded flash. UMC will also make this technology available to other companies through licensing with Avalanche Technology Inc.

Under the terms of the agreement, UMC will provide embedded non-volatile MRAM blocks based on UMC’s 28nm CMOS manufacturing process. This will enable customers to integrate low latency, very high performance and low power embedded MRAM memory blocks into MCUs and SoCs, targeting the Internet of Things, wearable, consumer, industrial and automotive electronics markets.

The two companies are also considering to expand the cooperation beyond 28nm, as Avalanche Technology’s CMOS compatibility and scalability to advanced process nodes enables integration of unified memory (non-volatile as well as SRAM) blocks into next generation highly integrated MCUs and SoCs. This allows system designers to maintain the same architecture and software ecosystem without a redesign.

“We’re excited to team with a world leader in semiconductor manufacturing such as UMC to bring this outstanding technology to market,” said Petro Estakhri, CEO and co-founder of Avalanche Technology.

“UMC is continuously introducing enhanced process offerings to bring added competitive benefits to our customers,” said G C Hung, vice president of Advanced Technology Development at UMC. “With embedded NVM becoming more prevalent in today’s IC designs, we have developed a strong portfolio of robust eNVM process solutions for high growth sectors such as emerging consumer and automotive applications. We are happy to cooperate with Avalanche Technology for 28nm MRAM, and we look forward to ramping this process to production for UMC customers.”

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Samsung Electronics starts mass production of industry’s first 4-bit consumer SSD

Samsung Electronics Co., Ltd. today announced that it has begun mass producing the industry’s first 4-bit (QLC, quad-level cell) 4-terabyte (TB) SATA solid-state drive (SSD) for consumers.

Based on 1-terabit (Tb)* V-NAND with outstanding performance equivalent to the company’s 3-bit design, Samsung’s QLC SSD is expected to bring a new level of efficiency to consumer SSDs.

“Samsung’s new 4-bit SATA SSD will herald a massive move to terabyte-SSDs for consumers,” said Jaesoo Han, executive vice president of memory sales & marketing at Samsung Electronics. “As we expand our lineup across consumer segments and to the enterprise, 4-bit terabyte-SSD products will rapidly spread throughout the entire market.”

With its new 1Tb 4-bit V-NAND chip, Samsung will be able to efficiently produce a 128GB memory card for smartphones that will lead the charge toward higher capacities for high-performance memory storage.

Typically, as data stored within a memory cell increases from three bits to four, the chip capacity per unit area would rise and the electrical charge (used to determine information from a sensor) would decrease by as much as 50 percent, making it considerably more difficult to maintain a device’s desired performance and speed.

However, Samsung’s 4-bit 4TB QLC SATA SSD maintains its performance levels at the same level as a 3-bit SSD, by using a 3-bit SSD controller and TurboWrite technology, while increasing drive capacity through the use of 32 chips, all based on 64-layer fourth-generation 1Tb V-NAND.

The 4-bit QLC SSD enables a sequential read speed of 540 MB/s and a sequential write speed of 520 MB/s, and comes with a three-year warranty.

Samsung plans to introduce several 4-bit consumer SSDs later this year with 1TB, 2TB, and 4TB capacities in the widely used 2.5-inch form factor.

Since introducing the 32-gigabyte (GB) 1-bit SSD in 2006, which ushered in the PC SSD era, to today’s 4TB 4-bit SSD, Samsung continues to drive new thresholds for each multi-bit generation.**

In addition, the company expects to provide M.2 NVMe SSDs for the enterprise this year and begin mass production of 4-bit fifth-generation V-NAND. This will considerably expand its SSD lineup to meet the growing demand for faster, more reliable performance across a wide span of applications, such as next generation data centers, enterprise servers, and enterprise storage.

* 1Tb (128GB) x 32 = 4TB (4,096GB)

** Samsung’s mass production history of SSDs in bits per cell

Year Bit Nodes Chip Capacity Drive Capacity
2006 1-bit SLC (single-level cell) 70nm-class 4Gb 32GB
2010 2-bit MLC (multi-level cell) 30nm-class 32Gb 512GB
2012 3-bit TLC (triple-level cell) 20nm-class 64Gb

500GB

2018 4-bit QLC (quad-level cell) 4th-gen V-NAND 1Tb 4 TB

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Energy harvesting semiconductor content to approach $3.4B by 2022, says Semico Research

The term energy harvesting, also known as power scavenging, is used to describe the creation of energy derived from a variety of external sources such as solar power, thermal energy, wind energy, kinetic energy or electromagnetic sources. Energy harvesters accumulate the wasted energy in a system, such as heat given off by motors or semiconductors, or the vibrations of motors or other moving objects. The basic technologies for generating energy are: mechanical vibration (kinetic energy), thermoelectric, solar (photovoltaic), and RF/Inductive.  A new research report from Semico Research Energy Harvesting: Reaping the Abundant Market, estimates that the semiconductor content for energy harvesting solutions will explode to $3.4 billion by 2022.

“While there is a great deal of interest in the different types of energy harvesting devices or energy generators, the greater opportunity for the semiconductor industry is the overall solution which includes power conversion, power management, microcontrollers, radios and MEMS sensors,” says Joanne Itow, Semico’s Manager of Manufacturing Research. “The advent of IoT with remote monitoring and data collection has also prompted more interest in energy harvesting as a viable solution to maintain WSNs (Wireless Sensor Networks).”

Key findings of the report include:

  • The number of devices with an energy harvesting solution will reach 509 million units by 2022.
  • Consumer devices (including toys) with energy harvesting accounted for 8 million units in 2017.
  • Bridges are expected to be a large user of energy harvesting in the infrastructure sector by 2022.
  • Energy harvesting devices in all buildings is expected to have a CAGR of 20.7% by 2022.

In its recent report Energy Harvesting: Reaping the Abundant Market” (MP112-18), Semico Research examines the market opportunity for energy harvesting outside of large solar installations and commercial power generation. A broad range of markets will employ energy harvesting to either replace batteries or extend battery life. These applications cover wireless sensor nodes (WSN) for bridges, infrastructure, building automation and controls, home automation (including lighting, security and environmental), automotive applications, cell phones, wearables and other consumer electronics. The report is 98 pages long and includes 13 tables and 37 figures.

Companies cited in the report include:

Analog Devices, Microchip (Atmel), CHERRY/ZF, Cymbet, Cypress, EnOcean, e-peas, Analog Devices/Linear Technology, Maxim Integrated, Microchip Technology, Powercast, Renesas, Semtech, Silicon Labs, Silicon Reef, STMicroelectronics, Texas Instruments, Ilika, Imprint Energy, Sakti3, Solid Power, Apple, Laird, microGen, Micropelt, Perpetuum, Piezo Systems, Sanyo, Thermo Life, Thermogen Technologies, EH Solution Providers, LORD Microstrain®, National Instruments, Nikola Labs, Phase IV Engineering, Resensys, Soundpower Corp., Eta Compute, Mentor Graphics, and X-FAB.

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Entegris EUV 1010 Reticle Pod receives ASML qualification

Entegris, Inc. (NASDAQ: ENTG) today released the next generation EUV 1010 Reticle Pod for high-volume IC manufacturing using extreme ultraviolet (EUV) lithography. Developed in close collaboration with ASML, one of the world’s largest manufacturers of chip-making equipment, Entegris’s EUV 1010 is the first to be qualified by ASML for use in the NXE:3400B and beyond.

As the semiconductor industry begins ramping EUV lithography for the high-volume manufacturing (HVM) of advanced technology nodes, keeping EUV reticles defect-free is more demanding than ever.  Entegris’s EUV 1010 Reticle Pod is now fully qualified by ASML for their latest generation scanner having demonstrated outstanding protection of the EUV reticles, including against the most critical particle challenges.  As a result, Entegris’s EUV 1010 enables customers to safely transition to smaller and smaller line widths, as needed for the most advanced lithography processes.

To achieve these levels of performance within the NXE:3400B scanner, Entegris developed new technologies for contacting the reticles and controlling the environment. “The Entegris EUV 1010 represents a significant breakthrough in improving defectivity so customers implementing HVM for advance technology nodes can focus on increasing efficiency and throughput,” said Paul Magoon, vice president of wafer and reticle handing for Entegris. “Development and testing with ASML ensures that EUV 1010 has been qualified for the most advanced EUV scanner available.”

Entegris is ISO 9001 certified and has manufacturing, customer service and/or research facilities in the United States, China, France, Germany, Israel, Japan, Malaysia, Singapore, South Korea and Taiwan.

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SEMI High-Tech Facility events: Shaping the future of smart factories in Taiwan

By Iris Tsou

The march to greater precision, efficiency and safety – the lifeblood of high-technology manufacturing facilities – has taken on a new urgency as emerging applications such artificial intelligence (AI), the Internet of Things (IoT) and Industry 4.0 give new meaning to smart factories. Facing fiercer competition and ever more sophisticated fabrication processes, semiconductor fabs are under intense pressure to keep pace with new technologies as they work to upgrade. Nowhere are the stakes higher than in Taiwan, where high-tech manufacturing contributes mightily to the region’s GDP growth.

To help Taiwan fabs confront the challenges and opportunities of designing smarter factories, SEMI and its High-Tech Facility Committee hosted the High-Tech Facility Workshop in June. SEMICON Taiwan 2018 High-Tech Facility Pavilion exhibitors gathered to explore how they can build smarter factories by deploying smart surveillance and disaster prevention technologies along with smart communications systems that better use manufacturing data to drive new safety and product quality efficiencies.

During the workshop, SEMI High-Tech Facility Committee representatives shared strides it has made upgrading overseas facilities and developing standards to help establish smart factories in Taiwan.

SEMICON Taiwan – 5-7 September at Taipei’s Nangang Exhibition Center – is also an important event for advancing smart manufacturing in Taiwan. Nearly 30 leading global manufacturers will exhibit at the SEMICON Taiwan High-Tech Facility Pavilion. The venue covers operational aspects of semiconductor manufacturing vital to becoming smarter including energy savings, nano-contamination control, facility information modeling, precision instrumentation and control, fire protection, mechatronics, and automation control. The pavilion will also feature a series of theme events offering a comprehensive overview of topics including the latest practices for integrating smart facility capabilities from the perspective of an advanced fab designer.

At the TechXPOT stage, High-Tech Facility Pavilion exhibitors will also demonstrate the latest technology breakthroughs and cutting-edge smart factor solutions.

The September 6th High-Tech Facility International Forum at SEMICON Taiwan will again gather factory experts and thought leaders from industry and academia to examine “Effective Ways to Make a Facility Smart.“ Experts from industry heavyweights in the fields of wafer foundry, LCD, memory and semiconductor packaging including TSMC, UMC, Innolux, ASE, Micron Taiwan, Winbond and VIS will offer insights into key areas of high-tech facilities including facility electricity, machinery, water management, vaporization and automation systems. On the same day as the forum, the High-Tech Facility Get-Together and High-Tech Facility VIP Dinner will bring together industry elites, academic professionals, and government officials to explore partnership opportunities.

SEMI Taiwan and the High-Tech Facility Committee share HTF market trends information, technology updates and standards with SEMI members and exhibitors.

Founded in 2013, the High-Tech Facility Committee now has 85 corporate members. Dedicated to accelerating industry collaboration through the integration of Taiwan industrial, government and academic resources, the committee each year holds several group meetings focusing on topics including energy savings, earthquake and fire protection, nano-contamination control, and precision instrumentation and control to advance critical technologies and facilitate standardization. The committee also aims to help the industry become more competitive faster by promoting technology standards that boost productivity and reduce production costs.

Please visit www.semi.org and www.semicontaiwan.org for more information about SEMI’s high-tech facility initiatives.

Iris Tsou is a marketing specialist at SEMI Taiwan. 

Originally published on the SEMI blog.

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The rebirth of the semiconductor industry

By Ajit Manocha

At a Glance

“Software is eating the world … and AI is eating software.” Amir Husain, author of The Sentient Machine, at SEMICON West 2018

We’re living in a digital world where semiconductors have been taken for granted. But, Artificial Intelligence (AI) is changing everything – and bringing semiconductors back into the deserved spotlight. AI’s potential market of hundreds of zettabytes and trillions of dollars relies on new semiconductor architectures and compute platforms. Making these AI semiconductor engines will require a wildly innovative range of new materials, equipment, and design methodologies.

Moore’s Law carried us the past 50-plus years and as we’re now stepping into the dawn of AI’s potential, we can see that the coming Cognitive Era will drive its own exponential growth curve. This is great for the world – virtually every industry will be transformed, and people’s lives will get better – and it’s fantastic for our industry. This truly is the very best time to be working in our industry. I’m excited to be at SEMI in this inflection period and at the center of the collaborative platforms that bring the electronics manufacturing supply chain together to Connect, Collaborate, and Innovate to realize the new Cognitive Era. I invite you to partner with SEMI in building the foundation for the Cognitive Era to increase the growth and prosperity of our industry.

The World Wakes Up

Our lives have become digital. An Amazon Echo wakes us up and answers questions about the weather and traffic. Google Maps tells us the best way to get to a meeting. Yelp finds the best nearby restaurant. A Tweet now even informs us of the latest change in government policy. It’s a digital world that we live in – and the world already takes it for granted.

We in the industry know that the digital world only works because of the semiconductors we make and because of our integrated electronics manufacturing supply chain. We make the materials and equipment that, in turn, make the chips that become the beating hearts of the digital economy.

But, semiconductors have been largely invisible – hidden away under and inside a smart speaker, locked deep within a phone, buried in data centers and out of view. Meanwhile, the internet companies like Google, Amazon, Alibaba, Tencent, and Facebook stole the meaning of “Tech” and were given most of the credit for our digital world.

But, finally, things are changing – it’s all coming back to semiconductors!

AI Changing Everything

Over $400B in semiconductors were sold in 2017 – those unseen chips like hearts beating away in Apple computers, in mobile phones for online shopping and social media, and in televisions showing Netflix. Now internet companies Alphabet, Alibaba, Amazon, Facebook, Microsoft and others are rushing to develop their own chips. Silicon is back in the Silicon Valley! Hardware is, once again, the place to be. Why? We are now entering the epoch of Artificial Intelligence (AI) – and semiconductors, and new compute architectures, are the key to AI. At this moment, hardware, not software, is the AI enabler to make leaps in performance and to usher in new architectures to become brain-like with neural networks.

Beyond major AI chip investments like Google’s (Alphabet) $300M+ program to develop its Tensor Processing Unit (TPU) chip, there’s been a surge in new chip startups and VC funding. Last year, VCs (with corporate investors) invested more than $1.5B in new AI chip startups – doubling the rate from the prior year.

After years of consolidation, there is, as some have described, a “Cambrian Explosion” of semiconductor startups with names like Cerebras, Graphcore, Wave Computing, Horizon Robotics, Cambricon Technologies, and DeePhi from the US, Europe, and China. Cambricon (China) has already become the first AI chip “Unicorn” (startup valued $1B+) with a valuation of more than $2.5B after their recent Round B financing. It’s a new silicon world and a new race, as Cade Metz (The New York Times, 1/14/2018) said, “… everyone is starting from the same place: the beginning of a new market.”

Winning at AI is very big business. John Kelly, SVP Cognitive Solutions and Research at IBM, in his SEMICON West keynote earlier this month, said, we’re in the era of Artificial Intelligence with more than a $2T opportunity for AI decision making support on top of the $1.5T IT business in 2025. McKinsey estimates deep learning could account for between $3.5T and $5.8T in annual value.

As John Kelly presented, AI will transform entire industries – not just our personal devices and lives. The $2T AI decision making support opportunity in 2025 is projected to transform the major economy industries as follows:

Moore’s Law describes the exponential increase in the number of transistors per area that has driven growth, and has been the engine for digital innovation, through first the computer era and then the mobility era and now into the dawn of the data era. While the Dennard scaling approach to Moore’s Law may be slowing, the data-centric era continues to drive demand and the industry continues to find new ways to pack more transistors into less volume. Chip sales are forecast to pass $0.5T in 2019 and I predict they will surpass $1T before 2030.

It turns out the Smart is not enough – we must reach “Beyond Smart.”

Beyond Smart – The Cognitive Era

As we move further into the data-centric age, we see it is more than Big Data and AI, it is, instead, the dawn of a wholly new cognitive era. SEMICON West’s 2018 theme was “Beyond Smart” because we are standing at the inflection from sensors triggering actions (smart) to systems that learn and make decisions (cognitive). Devices are moving “beyond smart” to being “cognitive or aware.” Gary Dickerson (CEO of Applied Materials) at SEMICON West said, “… we are in the beginning of the first inning of a major inflection.”

Even in the early dawn of the cognitive era, the volume of data is simply astonishing. In the last 24 months, we create more than 90% of all historic digital data. By 2025 we expect AI to generate 160 zettabytes – with 80% of that unstructured data. Moore’s Law is an exponential, but as John Kelly points out, AI’s deep learning is driving its own exponential with performance/watt increasing 2.5X each year.

AI was the focus of SEMICON West’s Day 1 keynotes – and a common theme through much of the events programming. There was a common language in the keynotes by John Kelly, Gary Dickerson, and William Dally (Chief Scientist and SVP of Research NVIDIA), and others. We heard how AI is based on data, algorithms, and compute. I was inspired by these talks and for the potential for AI and the cognitive era.

Looking ahead, I believe data + algorithms + compute + machine learning = knowledge and cognition. My vision is that this AI knowledge and cognition will be the catalyst to create new modes of systems transformations that will usher in the next Industrial Revolution. As the 4th Industrial Revolution becomes a reality, I look forward to working with others in SEMI Think Tanks to imagine the 5th Industrial Revolution – and its opportunities for our industry. I believe that it will make our lives better, healthier, more prosperous, and more fulfilled.

A sentiment shared by many speakers at SEMICON West was – this is the most exciting time to be in the semiconductor manufacturing industry. Many wished they were just now starting in the industry as this is the most interesting inflection and transformation ever. There is a flood of new architectures, new materials, new equipment, new processes – and a new system-based design approach to enable the Cognitive Era. We, in hardware manufacturing, are in the driver’s seat for this incredible ride.

SEMI is working to help its members speed their time to better business results – and to take full advantage of the Cognitive Era and AI opportunity. At SEMICON West 2018, SEMI provided a broad and deep slate of program education and spotlighted AI expertise across the electronics manufacturing supply. In case you missed it, SEMI also provided

  • Seven keynotes and dozens of expert panelists
  • Semiconductor venture funding program – problems and solutions for the ecosystem
  • SEMI Smart Workforce Pavilion with over 600 students registered to learn about the industry
  • Smart Pavilions including Smart Manufacturing and Smart Automotive

SEMI highlighted the five key vertical application platforms where our industry needs to collaborate across the full supply chain and streamline the supply chain for efficiency. The five are: IoT, Smart Transportation, Smart Manufacturing, Smart MedTech, and Smart Data. These verticals drive huge business potential and are just one of the reasons that SEMICON West has become the gathering place of the extended electronics manufacturing supply chain.

With SEMI, together we can realize the potential of the coming Cognitive Era. SEMI members can advance the industry with SEMI collective action in Workforce Development, Advocacy (public policy and regulatory), Standards to synchronize the industry, and in the many SEMI technology communities and special interest groups – to increase the global industry’s rate of growth and overall level of prosperity. For more information, please visit www.semi.org; to become a member, please visit http://www.semi.org/en/become-member-join-semi.

Ajit Manocha is President and CEO of SEMI

Originally published on the SEMI blog.

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Leti and CMP announce world’s first multi-project wafer service with integrated silicon OxRAM

Leti, a research institute at CEA Tech, and CMP, a service organization that provides prototyping and low-volume production of ICs and MEMS, today announced the integrated-circuit industry’s first multi-project-wafer (MPW) process for fabricating emerging non-volatile memory OxRAM devices on a 200mm foundry base-wafer platform.

Available on Leti’s 200mm CMOS line, the MPW service provides a comprehensive, very low-cost way to explore techniques designed to achieve miniaturized, high-density components. Including Leti’s Memory Advanced Demonstrator (MAD) future mask set with disruptive OxRAM (oxide-based resistive RAM) technology, Leti’s integrated silicon memory platform is developed for backend memories and non-volatility associated with embedded designs. The new technology platform will be based on HfO2/Ti (titanium-doped hafnium oxide) active layers.

Emerging OxRAM non-volatile memory is one of the promising technologies to be implemented for classical embedded memory applications on advanced nodes like micro-controllers or secure products, as well as for AI accelerators and neuromorphic computing.

Leti’s MAD platform is dedicated to advanced non-volatile memories, bringing both versatility and robustness for material and interface assessment, and allowing in-depth exploration of memory performance from technology and design perspectives.

The full platform’s highlights:

  • 200mm STMicroelectronics HCMOS9A base wafers in 130nm node
  • All routing is made on ST base wafers from M1 to M4 (included)
  • Leti’s OxRAM memory module is fabricated on top
  • One level of interconnect (i.e. M5) plus pads are fabricated in Leti’s cleanroom.

“Leti has developed during the past 20 years deep expertise in non-volatile memory (NVM) devices covering flash evolutive solutions and disruptive technologies,” said Etienne Nowak, head of the Leti’s Advanced Memory Lab. “This MPW capability, combined with our Memory Advanced Demonstrator platform, is based on a broad tool box that enables customized research with our partners, and provides a benchmark between different NVM solutions.”

The MPW service with integrated silicon OxRAM addresses all the key steps of advanced memory development. These include material engineering and analysis, developing critical memory modules, evaluation of memory cells coupled with electrical tests, modeling and innovative design techniques to comply with circuit design opportunities and constraints. This technology offer comes with a design kit, including layout, verification and simulation capabilities. Libraries are provided with a comprehensive list of active and passive electro-optical components. The design kit environment is compatible with all offers through CMP.

Providing access to a non-volatile memory process from Leti is a major achievement in development work at CMP. Since 2003, the organization has participated in national and European projects for developing access to NVM technologies (Mag-SPICE, Calomag, Cilomag, Spin, and Dipmem). With this new offer in place, the CMP users’ community can have the benefits and advantages of using this process through this close collaboration between CMP and Leti.

“CMP has a long experience providing smaller organizations with access to advanced manufacturing technologies, and there is very strong interest in the CMP community in designing and prototyping ICs using this process,” said Jean-Christophe Crébier, director of CMP. “It is an opportunity for many universities, start-ups and SMEs in France, Europe,North America and Asia to take advantage of this new technology and MPW service.”

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